EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 245
![IC CYCLONE III FPGA 16K 484FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP3C16F484C7N
Manufacturer Part Number
EP3C16F484C7N
Description
IC CYCLONE III FPGA 16K 484FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
7.EP3C16F484C7N.pdf
(274 pages)
Specifications of EP3C16F484C7N
Number Of Logic Elements/cells
15408
Number Of Labs/clbs
963
Total Ram Bits
516096
Number Of I /o
346
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Cyclone III
Number Of Logic Blocks/elements
15408
# I/os (max)
346
Frequency (max)
437.5MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
15408
Ram Bits
516096
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
No. Of Logic Blocks
963
Family Type
Cyclone III
No. Of I/o's
346
I/o Supply Voltage
3.3V
Operating Frequency Max
437.5MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2473
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP3C16F484C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C10M164C8N PDF datasheet #6
- EP3C16F484C7N PDF datasheet #7
- Current page: 245 of 350
- Download datasheet (8Mb)
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Remote System Upgrade
Table 9–28. Remote System Upgrade Current State Logic Contents In Status Register
© December 2009
Current State Logic
Factory information
Application information
part 1
Application information
part 2
Notes to
(1) The MSEL pin setting is in the AS or AP configuration scheme.
(2) The RSU master state machine is in factory configuration.
(3) The RSU master state machine is in application configuration.
(3)
(3)
Table
9–28:
Altera Corporation
(2)
■
■
Table 9–28
remote system upgrade master state machine is in factory configuration or
application configuration accessing the factory information or application
information respectively, and the MSEL pin setting is set to AS or AP configuration
scheme. The status register bit in
The previous two application configurations are available in the previous state
registers (previous state register 1 and previous state register 2), but only for
debugging purposes.
Table 9–29
2 in the status register when the MSEL pin setting is set to the AS or AP scheme. The
status register bit in
previous state register 1 and previous state register 2 have the same bit definitions.
The previous state register 1 reflects the current application configuration and the
previous state register 2 reflects the previous application configuration.
External configuration reset (nCONFIG) assertion
User watchdog timer time out
Status Register Bit
lists the contents of the current state logic in the status register, when the
lists the contents of the previous state register 1 and previous state register
31:30
29:24
31:30
31:30
29:24
23:0
28:0
23:0
29
Table 9–29
Master State Machine
current state
Reserved bits
Boot address
Master State Machine
current state
User watchdog timer
enable bit
User watchdog timer
time-out value
Master State Machine
current state
Reserved bits
Boot address
shows the bit positions in a 31-bit register. The
Table 9–28
Definition
lists the bit positions in a 32-bit logic.
The current state of the RSU master
state machine
Padding bits that are set to all 0's
The current 24-bit boot address that was
used by the configuration scheme as the
start address to load the current
configuration.
The current state of the RSU master
state machine
The current state of the user watchdog
enable, which is active high
The current entire 29-bit watchdog time-
out value
The current state of the RSU master
state machine
Padding bits that are set to all 0’s
The current 24-bit boot address that was
used by the configuration scheme as the
start address to load the current
configuration
(Note 1)
Cyclone III Device Handbook, Volume 1
Description
9–85
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