EP3C16F484C7N Altera, EP3C16F484C7N Datasheet - Page 98

• Manufacturer Part Number: EP3C16F484C7N
• Description: IC CYCLONE III FPGA 16K 484FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C16F484C7N

• Number Of Logic Elements/cells: 15408
• Number Of Labs/clbs: 963
• Total Ram Bits: 516096
• Number Of I /o: 346
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 15408
• # I/os (max): 346
• Frequency (max): 437.5MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 15408
• Ram Bits: 516096
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• No. Of Logic Blocks: 963
• Family Type: Cyclone III
• No. Of I/o's: 346
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 437.5MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200P0037 - BOARD DEV/EDUCATION ALTERA DE0544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2473

5–34
Table 5–11. Chapter Revision History (Part 2 of 2)
Cyclone III Device Handbook, Volume 1
July 2007
March 2007
Date
Version
1.1
1.0
Updated document with EP3C120 information.
■
■
■
■
■
■
■
Initial release.
Updated Table 5–1 and Table 5–4 with EP3C120 information.
Updated “Clock Control Block” section.
Updated locked signal information in “PLL Control Signals” section and added
Figure 5–16.
Updated “Manual Override” section, updated “Manual Clock Switchover”
section.
Added new “Programmable Bandwidth” section with Figure 5–21 and
Figure 5–22.
Replaced Figure 5-30 with correct diagram.
Added chapter TOC and “Referenced Documents” section.
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
Changes Made
© December 2009 Altera Corporation
Chapter Revision History