ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 111

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12.0
ENC424J600/624J600 devices are capable of operation
at 10Base-T and 100Base-TX speeds in Half-Duplex
and Full-Duplex modes for each. The speed and Duplex
mode can be selected manually, or the part can be
configured to automatically select the optimum link
parameters based on the capabilities of the link partner.
When operating in 10Base-T mode, the part also
compensates for incorrect polarity on the TPIN+/- pins
(100Base-TX signalling is non-polarized).
In half-duplex operation, only one Ethernet controller
may transmit on the physical medium at any given time.
If the host controller initiates a transmission while
another device is transmitting, the ENCX24J600 will
delay until the remote transmitter finishes its packet.
Other devices on the medium should do the same while
the ENCX24J600 is transmitting. If two controllers
begin transmitting at about the same time, a collision
will occur. In this case, the data on the medium is
corrupt; the ENCX24J600 aborts transmission and
attempts to retransmit later.
In full-duplex operation, both nodes may transmit
simultaneously, so collisions do not occur. For details
about transmitting packets, including collision detection
and correction, refer to Section 9.1 “Transmitting
Packets” .
Speed and Duplex modes are configured in the
PHCON1 register (Register 12-1). The PHSTAT1,
PHSTAT2 and PHSTAT3 registers (Registers 12-2
through 12-4) provide additional information about the
status of the link. The PHANA, PHANLPA and PHANE
registers
information
configuration.
12.1
Speed and Duplex modes can be manually selected by
disabling auto-negotiation. Manual configuration is
enabled by clearing the ANEN bit (PHCON1<12>).
When manual configuration is used, both the Speed
and Duplex mode must be selected. Set the SPD100
bit (PHCON1<13>) to select 100Base-TX operation or
clear SPD100 to select 10Base-T mode. Set the
PFULDPX bit (PHCON1<8>) to configure Full-Duplex
mode or clear PFULDPX to use half-duplex operation.
 2010 Microchip Technology Inc.
SPEED/DUPLEX
CONFIGURATION AND
AUTO-NEGOTIATION
Manual Configuration
(Registers 12-5
about
auto-negotiation
through 12-7)
status
contain
and
ENC424J600/624J600
After reconfiguring the Speed and Duplex modes,
update the MACON2, MACLCON, MAIPG and
MABBIPG registers as described in Section 8.9 “After
Link Establishment” .
12.2
Auto-negotiation allows Ethernet devices to agree
upon the fastest supported transmission rate. When an
Ethernet link is broken, a series of Fast Link Pulses
(FLPs) are transmitted periodically to initiate a link.
Among other things, these pulses encode information
about the node’s speed and duplex capabilities.
If a remote partner exists and supports auto-negotiation,
it will reply with a burst of FLPs to advertise its own link
capabilities. If both devices support 100Base-TX full
duplex, the link will be established and that mode will be
used. Otherwise, the link falls back to 100Base-TX half
duplex, 10Base-T full duplex or 10Base-T half duplex, in
that order.
If the remote link partner does not support auto-
negotiation, the device will use an algorithm known as
Parallel Detection to determine if the link partner is a
10Base-T device or 100Base-TX device. Parallel
Detection will optimally resolve the operating speed,
however, it will not have any means of learning the
duplex state of the remote node. Therefore, the
ENCX24J600 PHY will always resort to the half-duplex
state when auto-negotiation is not available. A duplex
mismatch will occur if the remote device is operating in
Full-Duplex mode. To determine whether or not the
remote link supports auto-negotiation, check the value
of the LPANABL bit (PHANE<0>).
Auto-negotiation is enabled by default at power-up, but
can be disabled by clearing the ANEN bit. To restart the
auto-negotiation process, set RENEG (PHCON1<9>).
After setting RENEG, the hardware automatically clears
this bit to ‘ 0 ’ immediately.
During auto-negation, the information in the PHANA
register is advertised to the link partner by transmitting
the information encoded in the Fast Link Pulses. The
ANDONE bit (PHSTAT1<5>) is set by the hardware
when the auto-negotiation process completes. The
value of SPDDPX<2:0> (PHSTAT3<4:2>) indicates
which operation mode has been selected. The remote
link partner’s capabilities are also stored in the
PHANLPA register.
Note:
Auto-Negotiation
When
SPD100 (PHCON1<13>) and PFULDPX
(PHCON1<8>) are control only bits. They
have no effect on Speed or Duplex modes
and do not indicate the current selection
when read.
auto-negotiation
DS39935C-page 109
is
enabled,