ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 34

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
3.4
The cryptographic data memory is used to store key
and data information for the Modular Exponentiation,
AES and MD5/SHA-1 hashing engines. The RAM for
these modules is actually implemented inside of the
modules themselves; this allows fast memory access
for the access-intensive encryption engines, as well as
the simultaneous use of more than one module by an
application. This memory is mapped into an area of
address space that is accessible only by the DMA
controller. The host controller must write to the crypto-
graphic data memory by writing data to the 24-Kbyte
SRAM buffer, then using the DMA to copy it into the
security engine. Reading is performed in the opposite
order, using the DMA to copy the data out of the
security engine and into the SRAM buffer.
The mapping of the cryptographic space is shown in
Figure 3-3. For additional information on the crypto-
graphic engines, refer to Section 15.0 “Cryptographic
Security Engines”. For additional information on the
DMA controller, see Section 14.0 “Direct Memory
Access (DMA) Controller”.
FIGURE 3-3:
DS39935C-page 32
Cryptographic Data Memory
Initialization Vector/State In
Length State Out (55 bits)
Length State In (55 bits)
Text A In/Out (128 bits)
Text B In/Out (128 bits)
(512, 768 or 1024 bits)
(128, 192 or 256 bits)
Data/Result (X/Y)
XOR Out (128 bits)
(up to 1024 bits)
Digest/State Out
(128 or 160 bits)
(up to 1024 bits)
Unimplemented
Unimplemented
Encryption Key
Exponent (E)
Modulus (M)
(512 bits)
(160 bits)
Data In
CRYPTOGRAPHIC DATA
MEMORY MAPPING
DMA Pointers
7800h
787Fh
7880h
78FFh
7900h
797Fh
7A00h
7A3Fh
7A40h
7A53h
7A54h
7A5Bh
7A70h
7A83h
7A84h
7A8Bh
7C00h
7C1Fh
7C20h
7C2Fh
7C30h
7C3Fh
7C40h
7C4Fh
3.5
The SRAM buffer is a bulk 12K word x 16-bit (24 Kbytes)
memory, used for TX/RX packet buffering and general
purpose storage by the host microcontroller. In most
cases, the memory is accessed using a byte-oriented
interface, so the memory can normally be thought of as
a simple 24-Kbyte memory buffer divided into a general
purpose/TX area and an RX area (Figure 3-4).
FIGURE 3-4:
Ethernet
100Base-TX networks occur at a fixed speed of
10 Mbps or 100 Mbps, respectively. Intra-byte gaps are
not allowed. This requires the host controller to build
outbound transmit frames in their entirety in the SRAM
buffer before the hardware is allowed to begin trans-
mission. Similarly, when receiving packets, the buffer
provides space for the hardware to write the incoming
packet without forcing the host microcontroller to
immediately read and process the packet.
After the part exits Reset, the entire buffer is accessible
by the host controller, regardless of other transmit,
receive or DMA operations that may simultaneously
also be accessing the general purpose or receive
buffer memory.
SRAM Buffer
communications
General Purpose
Circular RX FIFO
Buffer
Buffer
SRAM BUFFER
ORGANIZATION
 2010 Microchip Technology Inc.
on
0000h
ERXST – 1
ERXST
5FFFh
10Base-T
and