ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 162

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
G
General Power-Down Sequence....................................... 137
H
Host Interface Pins........................................................ 13–15
I
I/O Level Shifting................................................................. 15
Initialization
INT Pin ................................................................................ 13
Internet Address................................................................ 162
Interrupts
INTIE
M
MAC Registers .................................................................... 19
Magnetics and External Components ................................. 11
MD5 Hashing .................................................................... 126
Memory Map
Microchip Internet Web Site .............................................. 162
Modular Exponentiation Engine ........................................ 125
N
N-Byte Instructions
O
Oscillator ............................................................................... 9
P
Packaging
Parallel Slave Port Interface (PSP)
PHY Register File Summary ............................................... 31
PHY Registers..................................................................... 28
PHY Subystem Reset ......................................................... 74
DS39935C-page 160
After Link Establishment ............................................. 76
CLKOUT Frequency ................................................... 75
MAC ............................................................................ 75
PHY............................................................................. 76
Receive Buffer ............................................................ 75
Receive Filters ............................................................ 75
Reset........................................................................... 75
Transmit Buffer ........................................................... 75
Sources ............................................................. 121–122
Wake-on-LAN/Remote Wake-up .............................. 122
Global Interrupt Enable Bit........................................ 117
Cryptographic Data Memory ....................................... 32
PSP............................................................................. 18
SPI .............................................................................. 17
SRAM Indirect Access Pointers .................................. 34
Banked SFR................................................................ 45
SRAM Buffer ............................................................... 49
Unbanked SFR ........................................................... 47
Details ....................................................................... 150
Marking ..................................................................... 149
External Connections .................................................. 14
Mode 1 ........................................................................ 53
Mode 10 ...................................................................... 69
Mode 2 ........................................................................ 55
Mode 3 ........................................................................ 57
Mode 4 ........................................................................ 59
Mode 5 ........................................................................ 61
Mode 6 ........................................................................ 64
Mode 9 ........................................................................ 67
Performance Considerations ...................................... 53
Physical Implementation ............................................. 51
Using The Interface..................................................... 52
Pin Functions
Pinout Descriptions........................................................... 7–8
Power-on Reset .................................................................. 73
Power-Saving Features .................................................... 137
PSP Mode Selection (table)................................................ 14
R
Reader Response............................................................. 163
Receive Filters .................................................................... 72
Receive Only Reset ............................................................ 74
Receiving Packets ........................................................ 86–87
Register Maps
A14:A0 .......................................................................... 7
AD15:AD0..................................................................... 7
AL ................................................................................. 7
B0SEL/B1SEL .............................................................. 7
CLKOUT ....................................................................... 7
CS/CS........................................................................... 7
EN................................................................................. 7
INT ................................................................................ 7
LEDA/LEDB .................................................................. 7
OSC1/OSC2 ................................................................. 8
PSPCFG4:PSPCFG0 ................................................... 8
RBIAS ........................................................................... 8
RD ................................................................................ 8
RW................................................................................ 8
SCK .............................................................................. 8
SI .................................................................................. 8
SO ................................................................................ 8
SPISEL ......................................................................... 8
TPIN+/TPIN- ................................................................. 8
TPOUT+/TPOUT- ......................................................... 8
V
V
V
V
V
V
WR................................................................................ 8
WRH/WRL .................................................................... 8
Broadcast Collection................................................. 100
CRC Error Collection/Rejection .................................. 99
Hash Table Collection............................................... 100
Magic Packet Collection ........................................... 101
Multicast Collection................................................... 100
Not-Me Unicast Collection .......................................... 99
Pattern Match Collection........................................... 102
Pattern Match Collection (example).......................... 103
Promiscuous Mode ................................................... 102
Runt Error Collection/Rejection .................................. 99
Unicast Collection ....................................................... 99
Configuring Reception ................................................ 87
ERXHEAD/ERXTAIL Buffer Wrap (example) ............. 86
Incoming Packet Storage............................................ 87
Receive Status Vector ................................................ 89
Receive Status Vector (RSV) ..................................... 87
Received Packet in Buffer Memory (example) ........... 88
Status Vectors ............................................................ 89
CLR (8-Bit PSP).......................................................... 24
SET (8-Bit PSP).......................................................... 23
SET/CLR (16-Bit PSP)................................................ 25
CAP
DD
DDOSC
DDPLL
DDRX
DDTX
/V
............................................................................. 8
SS
/V
/V
/V
/V
SSTX
SSRX
........................................................................ 8
SSPLL
SSOSC
................................................................. 8
................................................................ 8
.............................................................. 8
........................................................... 8
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