ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 45

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.5
All three-byte instructions are designed to quickly read
or update the Read and Write Pointers used to access
the SRAM buffer area. Unlike the single byte instruc-
tions and RBSEL, each instruction in this group has
distinct read and write implementations.
For read commands (shown in Figure 4-3), the opcode
byte (‘011xxx10’) must be presented on the SI pin,
MSb first, followed by “don’t care” values for the second
and third bytes (9
Response data is returned on the SO line during the
second and third bytes.
Data on the SO line is also presented in MSb first bit
ordering. However, read commands are intended to
read a 16-bit pointer in little-endian byte ordering.
Therefore, the first byte on the SO line (returned during
SCK clocks, 9 through 16) is the lower byte of the 16-bit
pointer and is followed by the upper byte (returned
during SCK clocks 17 through 24).
Read operations do not affect the ENCX24J600
device’s internal state, and therefore, can be aborted at
any time by deasserting chip select.
FIGURE 4-3:
FIGURE 4-4:
 2010 Microchip Technology Inc.
SCK
SCK
SO
CS
SO
CS
SI
SI
Three-Byte Instructions
Hi-Z
Hi-Z
th
x
x
1
0
1
0
through 24
THREE-BYTE READ INSTRUCTION TIMING
THREE-BYTE WRITE INSTRUCTION TIMING
2
1
x
2
1
x
3
1
x
3
1
x
Opcode
Opcode
c4 c3 c2 1
c4 c3 c2 0
4
4
x
x
th
5
x
5
x
SCK rising edges).
6
x
6
x
7
7
x
x
8
0
x
8
0
x
d7 d6 d5 d4 d3 d2 d1 d0
d7
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
x
d6
x
Read Low Byte
Write Low Byte
d5 d4 d3 d2 d1
x
x
ENC424J600/624J600
x
For write commands (shown in Figure 4-4), the opcode
byte (‘011xxx00’) must be presented on the SI line,
MSb first, followed immediately by the pointer data to
be written. Like the data returned during a read
operation, the write data must be presented MSb first,
Least Significant Byte first.
If the application only needs to write to the lower byte of
a 16-bit pointer, it can optionally skip the upper byte by
raising chip select after the 16
adequate chip select hold time to elapse. The hardware
would then update the lower byte of the pointer while
maintaining the original value in the upper byte.
During write operations, the device actively drives the
SO line while the chip select line is active. The value
during this interval is to be ignored.
All three-byte instructions, including read operations,
are considered to be finished at the end of the 24th
SCK clock (if reached). The host controller may issue
another SPI instruction or multiple fixed length
instructions without deasserting chip select.
There are 12 three-byte instructions, which are divided
equally between read and write instructions. They are
listed in Table 4-3.
x
x
d0
x
D7 D6 D5 D4 D3 D2 D1
D7 D6 D5
x
x
Read High Byte
Write High Byte
x
(optional)
(optional)
D4 D3 D2 D1 D0
x
x
th
x
clock pulse and allowing
x
DS39935C-page 43
D0
x
x
x
Hi-Z
Hi-Z