ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 59

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.3.3
PSP Mode 3 is a 16-bit, fully demultiplexed mode that
is available on 64-pin devices only. The parallel inter-
face consists of 16 bidirectional data pins (AD<15:0>)
and 8 to 14 separate address pins (A<13:0>). To select
PSP Mode 3, tie PSPCFG3 and PSPCFG4 to V
while connecting PSPCFG2 to V
the connections required.
An active-high RD strobe and two Write strobes (WRH
and WRL) are utilized in conjunction with a separate
Chip Select (CS). These four pins allow the host to
select the device, then signal when a read operation is
desired or when valid data is being presented to be
written on either the low byte, high byte or both. For
proper operation, do not assert CS and RD while
simultaneously asserting either WRL or WRH.
In PSP Mode 3, AD<15:0> stay in a high-impedance
state any time CS or RD are low.
To perform a read operation:
1.
2.
3.
FIGURE 5-7:
 2010 Microchip Technology Inc.
Raise the CS line (if connected to the host).
Present the address to be read onto the address
bus.
Raise the RD strobe and wait the required time
for the access to occur.
Note 1: Use of the CS strobe from the controller is optional. If not used, tie CS to V
MODE 3
2: WRL and WRH may optionally be tied together to form a 16-bit write strobe. See Section 5.2.3 “Write Select
3: Connect these pins when direct addressing of the entire SRAM buffer is required. Tie to V
4: Use of the external interrupt signal to the controller is optional.
Pins” for details.
addressing is desired.
DEVICE CONNECTIONS FOR PSP MODE 3
Host MCU
DD
PMD<15:0>
PMA<13:8>
. Figure 5-7 shows
PMA<7:0>
PMWRH
PMWRL
PMCSx
INTx
PMRD
(4)
SS
+3.3V
,
8
16
6
(2)
ENC424J600/624J600
When RD is raised high, the data bus begins driving out
indeterminate data for a brief period, then switches to
the correct read data after the appropriate read access
time has elapsed. When the RD strobe is lowered, the
data pins will return to a high-impedance state.
The device always outputs a full 16 bits of data for each
read request. If only 8 bits of data are required, read the
data from the correct pins (AD<15:8> or AD<7:0>) and
discard the remaining byte.
To perform a write operation:
1.
2.
3.
4.
5.
Sample timing diagrams for reading and writing data in
this mode are provided in Figure 5-8 and Figure 5-9,
respectively.
100 k 
Raise the CS line (if connected to the host).
Present the address onto the A<13:0> address
bus.
If writing to the low byte of the memory location,
present the data on AD<7:0>, and strobe the
WRL signal high and then low.
If writing to the high byte, present the data on the
AD<15:8> and strobe the WRH signal.
If writing a whole word, strobe both WRL and
WRH simultaneously.
CS
RD
WRL
WRH
A<13:8>
A<7:0>
AD<15:0>
INT/SPISEL
PSPCFG2
PSPCFG3
PSPCFG4
(1)
(2)
ENC624J600
(3)
DD
.
DD
when only indirect
DS39935C-page 57