ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 129

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Set the HASHEN (ECON1<14>) bit to enable the
module and begin transferring data. Once this bit is set,
all data copied to the module through the DMA will be
added to the hash calculation. Data should be written
beginning at the Hash Data In address, 7A00h. After
copying 64 bytes, the application must pause and wait
for the HASHIF (EIR<13>) bit to be set by the
hardware. This flag indicates that the hardware has
completed processing for that block. The application
should then clear the HASHIF flag and continue with
the next block, beginning transfers again at address
7A00h.
Before the final DMA transfer is started, the application
must set the HASHLST bit (ECON1<12>). When this
bit is set, and a DMA transfer is initiated to the hash
engine, the engine pads the input appropriately for the
selected algorithm and calculates the final result. Once
the HASHIF flag is set, the message digest is available
in Digest/State Out, beginning at address 7A70h.
The application must wait for the HASHIF flag after every
64-byte block, but all 64 bytes need not be transferred in
one operation. For example, it is possible to transfer
16 bytes in one operation and the remaining 48 in a sec-
ond. However, it is required that the DMA stop copying
data once a full 64-byte block is created. For example, if
16 bytes are transferred in one operation, and 52 in the
next (for a total of 68 bytes), then the final four bytes will
be lost and the output will be incorrect.
Note that the Hash Data In memory is not physically
implemented, nor is it accessible for reading. Transfers
to any address in the range of 7A00h to 7A3Fh instruct
the DMA to write directly to the hash engine. Therefore,
if 32 bytes are copied, beginning at 7A00h, a sub-
sequent write of 32 bytes to the same address will not
overwrite the previously written data. Instead, the two
32-byte writes are appended to form a single 64-byte
block and the hashing process begins. When making
multiple transfers as part of a single 64-byte block, the
second and subsequent transfers may begin, either at
their sequential location, or they may all use the same
destination address of 7A00h.
With the exception of the final transfer, all data transfers
to the hash engine must be of an integral length of
4 bytes. For example, chunks of 4, 8, 12, 16, etc. are
legal, while DMA transfers of length 1, 2, 3, 5, 6, 7, 9,
10, 11, etc. are illegal. Optimal DMA copy performance
is also achieved when the source address is word or
even aligned. To allow for hashes to be computed over
any length of data, the integral length of 4 restriction
does not apply to the last transfer (when HASHLST is
set).
 2010 Microchip Technology Inc.
ENC424J600/624J600
15.2.1
The module implements the MD5 function, as
described in the Internet Engineering Task Force
RFC 1321, “The MD5 Message Digest Algorithm” . The
resulting digest is 128 bits (16 bytes) in length and is
left-justified in the result space.
To calculate an MD5 digest:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Wait for HASHIF to be set.
11. Use the DMA to transfer the resulting 16-byte
12. Clear HASHEN.
Step 5 will take 500 ns from the time the DMA com-
pletes the transfer. Under worst case conditions, the
DMA will take 3.94  s to copy a block of 64 bytes after
the DMAST bit is set. Therefore, for maximum perfor-
mance, applications may choose to omit step 3 and
replace step 5 with a processor enforced wait of at least
4.5  s between the start of a DMA copy operation and
the start of the next DMA copy operation of 64 bytes.
Steps 7 and 10 may also be optimized. However, the
wait period should be extended to no less than 5.6  s
as the hardware requires extra time to perform an extra
padding step as required by the MD5 algorithm.
Step 9 can be split into multiple DMA copy transactions
if step 8 is held off until immediately before the very last
DMA copy operation is performed.
Clear SHA1MD5 (ECON2<12>), HASHOP
(ECON1<13>) and HASHLST (ECON1<12>).
Set HASHEN (ECON1<14>).
Clear HASHIF (EIR<13>).
Use the DMA to transfer exactly 64 bytes to
address 7A00h. This transfer may be split into
multiple transactions if each copy operation is
an integral length of 4 and the net of all transfers
is 64 bytes.
Wait for HASHIF to be set.
Repeat steps 3 through 5 until fewer than
64 bytes remain.
Clear HASHIF.
Set HASHLST (ECON1<12>).
Use the DMA to transfer the remaining bytes to
address 7A00h.
hash from address 7A70h. This 128-bit hash will
be in big-endian byte order.
MD5 HASHING
DS39935C-page 127