ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 76

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
7.3
A Transmit Only Reset is performed by setting the
TXRST bit (ECON2<6>). The transmit logic is held in
Reset until the bit is cleared. Any pending transmission
is aborted and TXRTS (ECON1<1>) is cleared. To
resume normal operation, clear the TXRST bit.
Both the POR and System Resets automatically perform
a Transmit Reset, so this step does not need to be per-
formed after a System or Power-on Reset. Only the
transmit logic is affected by this operation. Other register
and control blocks are not affected by this event.
7.4
A Receive Only Reset is performed by setting the
RXRST bit (ECON2<5>). The receive logic is held in
Reset until the bit is cleared. Any packet being received
is aborted and RXEN (ECON1<0>) is cleared. To
resume normal operation, clear the RXRST bit.
Both the POR and System Resets automatically perform
a Receive Reset, so this step does not need to be per-
formed after a System or Power-on Reset. Only the
receive logic is affected by this operation. Other register
and control blocks are not affected by this event.
Following a Receive Only Reset, it is necessary to
manually reconfigure the RX SFRs for normal receive
operation again. For example, applications must clear
the PKTCNT field in ESTAT by setting the PKTDEC bit
(ECON1<8>) enough times for the count to reach zero.
Similarly, applications must reset the ERXST and
ERXTAIL Pointers before enabling reception again with
the RXEN bit.
DS39935C-page 74
Transmit Only Reset
Receive Only Reset
Unlike the Transmit and Receive Only Resets, the PHY
hardware automatically clears the PRST bit. It is recom-
7.5
The PHY module may be reset by setting the PRST bit
(PHCON1<15>). The PHY register contents all revert
to their default values.
cannot be removed from Reset immediately after setting
PRST. The PHY requires a delay, after which the
mended that, after issuing a Reset, the host controller
polls PRST and waits for it to be cleared by hardware
before using the PHY.
The POR and System Resets automatically perform a
PHY Reset, so this step does not need to be performed
after a System or Power-on Reset. Only the PHY is
affected by this operation. Other register and control
blocks are not affected by this event.
PHY Subsystem Reset
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