ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 61

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.3.4
PSP Mode 4 is also a 16-bit, fully demultiplexed mode
that is available in 64-pin devices only. When using
PSP Mode 4, the parallel interface consists of
16 bidirectional data pins (AD<15:0>) and 8 to 14 sep-
arate address pins (A<13:0>). To select PSP Mode 4,
tie PSPCFG2 and PSPCFG4 to V
PSPCFG3 to V
required.
This mode uses a combined Read/Write (R/W) select,
two Byte Select (B0SEL and B1SEL) lines and a sepa-
rate Chip Select (CS) signal. These four pins allow the
host to select the device, indicate whether a read or
write operation is desired and signal when valid data is
being presented for writing on either the low byte, high
byte or both.
A logic-high signal on R/W indicates that a read opera-
tion is to be performed when either the B0SEL or
B1SEL strobe is asserted, while a logic low signal
indicates that a write operation is to be performed. The
state of R/W only affects the data bus state when either
B0SEL or B1SEL is active. When CS is driven low, R/W
is driven low, or both B0SEL and B1SEL are driven low
and the data bus stays in a high-impedance state.
To perform a read operation:
1.
2.
3.
FIGURE 5-10:
 2010 Microchip Technology Inc.
Raise the CS line (if connected to the host).
Raise the R/W signal.
Present the address to be read onto the address bus.
Note 1: Use of the CS strobe from the controller is optional. If not used, tie CS to V
MODE 4
2: B0SEL and B1SEL may optionally be tied together to form a 16-bit write strobe. See Section 5.2.3 “Write
3: Connect these pins when direct addressing of the entire SRAM buffer is required. Tie to V
4: Use of the external interrupt signal to the controller is optional.
SS
Select Pins” for details.
addressing is desired.
. Figure 5-10 shows the connections
DEVICE CONNECTIONS FOR PSP MODE 4
Host MCU
PMRD/PMWR
DD
PMD<15:0>
PMA<13:8>
PMA<7:0>
, while connecting
PMENB0
PMENB1
PMCSx
INTx
(4)
100 k 
8
16
6
(2)
ENC424J600/624J600
+3.3V
4.
When either BxSEL pin is raised high, the data bus
begins driving out indeterminate data for a brief period,
then switches to the correct read data after the appro-
priate read access time has elapsed. When B0SEL and
B1SEL are both low, the data bus pins return to a
high-impedance state.
The device always outputs a full 16 bits of data for each
read request, even if only one byte select is strobed. If
only 8 bits of data are required, read the data from the
correct pins (AD<15:8> or AD<7:0>) and discard the
remaining byte.
To perform a write operation:
1.
2.
3.
4.
5.
6.
Sample timing diagrams for reading and writing data in
this mode are provided in Figure 5-11 and Figure 5-12,
respectively.
Raise one or both byte select strobes.
Raise the CS line (if connected to the host).
Lower R/W.
Present the address onto the address bus.
If writing to the low byte of the memory location,
present the data on the AD<7:0>; then strobe
B0SEL high, then low.
If writing to the high byte, present the data on
AD<15:8> and strobe B1SEL.
If writing a whole word, strobe both B0SEL and
B1SEL simultaneously.
CS
R/W
B0SEL
A<13:8>
A<7:0>
AD<15:0>
INT/SPISEL
PSPCFG2
PSPCFG3
PSPCFG4
B1SEL
(1)
ENC624J600
(2)
(3)
DD
.
DD
when only indirect
DS39935C-page 59