ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 44

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
TABLE 4-2:
4.4
There is only one instruction in the ENCX24J600 com-
mand set which uses two SPI bytes. The Read Bank
Select opcode, RBSEL, reads the internal SFR bank
select state and returns the value to the host controller.
Figure 4-2 shows the timing relationships for perform-
ing the two-byte operation. The first byte of the opcode
(‘11001000’) must be presented on the SI pin, MSb
first, followed by “don’t care” values for the second byte
(9
FIGURE 4-2:
DS39935C-page 42
B0SEL
B1SEL
B2SEL
B3SEL
SETETHRST
FCDISABLE
FCSINGLE
FCMULTIPLE
FCCLEAR
SETPKTDEC
DMASTOP
DMACKSUM
DMACKSUMS
DMACOPY
DMACOPYS
SETTXRTS
ENABLERX
DISABLERX
SETEIE
CLREIE
th
Mnemonic
SCK
through 16
SO
CS
SI
Two-Byte Instructions
Hi-Z
th
1100 0000 Selects SFR Bank 0
1100 0010 Selects SFR Bank 1
1100 0100 Selects SFR Bank 2
1100 0110 Selects SFR Bank 3
1100 1010 Issues System Reset by setting ETHRST (ECON2<4>)
1110 0000 Disables flow control (sets ECON1<7:6> = 00)
1110 0010 Transmits a single pause frame (sets ECON1<7:6> = 01)
1110 0100 Enables flow control with periodic pause frames (sets ECON1<7:6> = 10)
1110 0110 Terminates flow control with a final pause frame (sets ECON1<7:6> = 11)
1100 1100 Decrements PKTCNT by setting PKTDEC (ECON1<8>)
1101 0010 Stops current DMA operation by clearing DMAST (ECON1<5>)
1101 1000 Starts DMA and checksum operation (sets ECON1<5:2> = 1000)
1101 1010 Starts DMA checksum operation with seed (sets ECON1<5:2> = 1010)
1101 1100 Starts DMA copy and checksum operation (sets ECON1<5:2> = 1100)
1101 1110 Starts DMA copy and checksum operation with seed (sets ECON1<5:2> = 1110)
1101 0100 Sets TXRTS (ECON1<1>), sends an Ethernet packet
1110 1000 Enables packet reception by setting RXEN (ECON1<0>)
1110 1010 Disables packet reception by clearing RXEN (ECON1<0>)
1110 1100 Enable Ethernet Interrupts by setting INT (ESTAT<15>)
1110 1110 Disable Ethernet Interrupts by clearing INT (ESTAT<15>)
SCK rising edges). The bank select
SINGLE BYTE INSTRUCTIONS
Opcode
x
TWO-BYTE INSTRUCTION TIMING (RBSEL OPCODE)
1
1
2
1
x
3
0
x
RBSEL Opcode
4
0
x
5
1
x
6
0
x
7
0
x
8
0
x
9
0
value (00h through 03h) is returned on the SO pin, MSb
first, while the second byte is being presented on the SI
pin.
Because this instruction is a fixed length with no
optional parameters, it is possible to execute any
instruction following the execution of RBSEL without
deasserting the chip select line in between.
Since this opcode does not modify the ENCX24J600
internal state, it can be aborted at any time by returning
the CS pin to the inactive state.
10
0
Instruction
11
0
SFR Bank Select
12
0
13
0
14
0
 2010 Microchip Technology Inc.
15
d
16
d
x
Hi-Z