ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 71

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.3.8
PSP Mode 10 is also a 16-bit, fully-multiplexed mode
that is available on 64-pin devices only. The parallel
interface consists of 16 bidirectional data pins
(AD<15:0>); the lower 14 (AD<13:0>) also function as
address pins. To select PSP Mode 10, tie PSPCFG1,
PSPCFG2 and PSPCFG3 to V
the connections required.
This mode uses an active-high Read/Write (R/W)
select and two Byte Select (B0SEL and B1SEL)
strobes in conjunction with separate Chip Select (CS)
and Address Latch (AL) inputs. These five pins allow
the host to select the device, latch an address, select
either a read or write operation, then assert the proper
Byte Select strobe(s) to perform the operation.
A logic high signal on the R/W pin indicates that a read
operation is to be performed when either the B0SEL or
B1SEL strobe is asserted, while a logic low signal
indicates that a write operation is to be performed. For
proper operation while the ENCX24J600 is selected,
the host controller should not assert AL while
simultaneously asserting either B0SEL or B1SEL.
The state of R/W only affects the AD<15:0> bus state
when either B0SEL or B1SEL is active. When CS is
driven low, R/W is driven low, or both B0SEL and
B1SEL are driven low, AD<15:0> stays in a
high-impedance state.
To perform a read operation:
1.
2.
3.
4.
5.
6.
FIGURE 5-22:
 2010 Microchip Technology Inc.
Raise CS (if connected to the host).
Present the address to be read onto AD<13:0>.
Strobe AL high, then low.
Raise R/W.
Set the host controller’s AD<15:0> bus pins as
inputs.
Raise either B0SEL or B1SEL, or both.
Note 1:
MODE 10
2:
3:
Use of the CS strobe from the controller is optional. If not used, tie CS to V
B0SEL and B1SEL may optionally be tied together to form a 16-bit write strobe. See Section 5.2.3 “Write Select Pins” for
details.
Use of the external interrupt signal to the controller is optional.
DEVICE CONNECTIONS FOR PSP MODE 1
Host MCU
DD
. Figure 5-22 shows
PMRD/PMWR
PMD<15:0>
PMENB0
PMENB1
PMCSx
PMALL
INTx
(3)
100 k
16
+3.3V
(2)
ENC424J600/624J600
When either BxSEL pin is raised high, the AD<15:0>
bus begins driving out indeterminate data for a brief
period, then switches to the correct read data after the
appropriate read access time has elapsed. When
B0SEL and B1SEL are both low, AD<15:0> return to a
high-impedance state.
The device always outputs a full 16 bits of data for each
read request, even if only one byte select is strobed. If
only 8 bits of data are required, read the data from the
correct pins (AD<15:8> or AD<7:0>) and discard the
remaining byte.
To perform a write operation:
1.
2.
3.
4.
5.
6.
7.
If a subsequent read or write of the same memory
address is desired, it is possible to restrobe B0SEL or
B1SEL without going through another address latch
cycle.
Sample timing diagrams for reading and writing data in
this mode are provided in Figure 5-23 and Figure 5-24,
respectively.
Raise CS (if connected to the host).
Present the address to write to on AD<13:0>.
Strobe AL.
Lower R/W.
If writing to the low byte of the memory location,
present the data on AD<7:0>, then strobe
B0SEL.
If writing to the high byte, present the data on
AD<15:8>, then strobe the B1SEL signal.
If writing a whole word, strobe both B0SEL and
B1SEL simultaneously.
AD<15:0>
INT/SPISEL
PSPCFG1
PSPCFG2
PSPCFG3
CS
R/W
B0SEL
B1SEL
AL
(1)
DD
ENC624J600
.
(2)
DS39935C-page 69