ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 24

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Symbolically, the names of the companion registers are
ENC424J600/624J600
TABLE 3-3:
3.2.4.1
A major difference between the SPI and PSP memory
maps is the inclusion of companion Bit Set and Bit
Clear registers for many of the E registers. Since the
PSP interface allows direct access to memory
locations, without a command interpreter, there are no
instructions
manipulations. Instead, this interface implements
separate Bit Set and Bit Clear registers, allowing users
to individually work with volatile bits (such as interrupt
flags) without the risk of disturbing the values of other
bits. Setting the bit(s) in one of these registers sets or
clears the corresponding bit(s) in the base register.
In the PSP interface, Bit Set and Bit Clear registers are
located in different areas of the addressable memory
space from their corresponding “base” SFRs. The
address of the registers is always at a fixed offset from
their corresponding base register. For the 8-bit interface,
the offset is 100h (Set) or 180h (Clear). For the 16-bit
interface, the offset is 80H (Set) or C0 (Clear).
the names of the base registers, plus the suffix form
“-SET” (or “-SETH/SETL”) for Bit Set registers and
“-CLR” (“-CLRH/CLRL”) for Bit Clear registers.
DS39935C-page 22
3F0A
3F0B
3F0C
3F0D
3F0E
Addr
3F00
3F01
3F02
3F03
3F04
3F05
3F06
3F07
3F08
3F09
3F0F
ERXHEAD
EDMALEN
EDMADST
ETXWIRE
ETXSTAT
EDMAST
EDMACS
EUDAND
ERXTAIL
EUDAST
ETXLEN
ECON1
ERXST
ETXST
ESTAT
Name
EIR
PSP Bit Set and Bit Clear Registers
implemented
ENC424J600/624J600 SFR MAP (BASE REGISTER MAP, 16-BIT PSP INTERFACE)
3F1A
3F1B
3F1C
3F1D
3F1E
Addr
3F10
3F12
3F13
3F14
3F15
3F16
3F17
3F18
3F19
3F1F
3F11
to
ERXFCON
perform
EUDAND
EUDAST
EPMM1
EPMM2
EPMM3
EPMM4
EPMCS
ECON1
ESTAT
EPMO
Name
EHT1
EHT2
EHT3
EHT4
EIR
single
3F2A
3F2B
3F2C
3F2D
3F2E
Addr
3F20
3F21
3F22
3F23
3F24
3F25
3F26
3F27
3F28
3F29
3F2F
bit
MIREGADR
MACLCON
MABBIPG
MACON1
MACON2
MAMXFL
Reserved
Reserved
Reserved
EUDAND
EUDAST
ECON1
MAIPG
MICMD
ESTAT
Name
EIR
Most SFRs have their own pair of Bit Set and Bit Clear
registers. However, these SFRs do not:
• MAC registers, including MI registers for PHY
• Read-only status registers (ERXHEAD, ETXSTAT,
• All of the SRAM Buffer Pointers and data windows
The Bit Set and Bit Clear registers for the 8-bit PSP
interface are listed in Table 3-4 and Table 3-5,
respectively. The registers for the 16-bit interface are
listed together in Table 3-6.
access
ETXWIRE and ESTAT)
(SFRs located at 7E80h to 7E9Fh in the 8-bit
interface, or 3F40h to 3F4Fh in the 16-bit
interface)
3F3C
3F3D
Addr
3F30
3F31
3F32
3F33
3F34
3F35
3F36
3F38
3F3A
3F3B
3F3E
3F3F
3F37
3F39
MAADR3
MAADR2
MAADR1
EUDAND
EUDAST
ERXWM
EIDLED
MISTAT
ECON2
ECON1
EPAUS
ESTAT
MIWR
Name
MIRD
EIE
EIR
 2010 Microchip Technology Inc.
Addr
3F4A
3F4B
3F4C
3F4D
3F4E
3F4F
3F40
3F41
3F42
3F43
3F44
3F45
3F46
3F47
3F48
3F49
EUDAWRPT
EUDARDPT
EUDADATA
EGPWRPT
ERXWRPT
EGPRDPT
ERXRDPT
EGPDATA
ERXDATA
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Name
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