ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 19

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.0
All memory in ENC424J600/624J600 devices is
implemented as volatile RAM. Functionally, there are
four unique memories:
• Special Function Registers (SFRs)
• PHY Special Function Registers
• Cryptographic Data Memory
• SRAM Buffer
The SFRs configure, control and provide status
information for most of the device. They are directly
accessible through the I/O interface.
The PHY SFRs configure, control and provide status
information for the PHY module. They are located
inside the PHY module and isolated from all other
normal SFRs, so they are not directly accessible
through the I/O interface.
The cryptography data memory is used to store key
and data material for the modular exponentiation, AES
and MD5/SHA-1 hashing engines. This memory area
can only be accessed through the DMA module.
The SRAM buffer is a bulk 12K x 16-bit (24 Kbyte) RAM
array used for TX and RX packet buffering, as well as
general purpose storage by the host microcontroller.
Although the SRAM uses a 16-bit word, it is
byte-writable. This memory is indirectly accessible
through pointers on all I/O interfaces. It can also be
accessed directly through the PSP interfaces.
3.1
Depending on the I/O interface selected, the four
memories are arranged into two or three different memory
address spaces. When the serial interface is selected, the
memories are grouped into three address spaces. When
one of the parallel interfaces is selected, they are
arranged into two address spaces. In all cases, the PHY
SFRs reside in their own memory address space.
FIGURE 3-1:
 2010 Microchip Technology Inc.
SFR Area
PHY Register
Area
MEMORY ORGANIZATION
I/O Interface and Memory Map
Unbanked Opcodes
Banked Opcodes
(inaccessible using
banked opcodes)
ENC424J600/624J600 MEMORY MAP WITH SPI INTERFACE
Unbanked
Bank 0
Bank 1
Bank 2
Bank 3
16-Bit, MIIM Access Only
00h
1Fh
00h
1Fh
00h
1Fh
00h
1Fh
1Fh
3Fh
5Fh
7Fh
9Fh
00h
20h
40h
60h
80h
MIREGADR
ENC424J600/624J600
3.1.1
When the SPI interface is selected, the device memory
map is comprised of three memory address spaces
(Figure ):
• the SFR area
• the main memory area
• the PHY register area
The SFR area is directly accessible to the user. This is
a linear memory space that is 160 bytes long. For
efficiency, the SFR area can be addressed as four
banks of 32 bytes each, starting at the beginning of the
space (00h), with an additional unbanked area of
32 bytes at the end of the SFR memory. Banked
addressing allows SFRs to be addressed with fewer
address bits being exchanged over the serial interface
for each transaction. This decreases protocol overhead
and enhances performance. SFRs can also be directly
addressed by their 8-bit unbanked addresses using
unbanked SPI commands. This allows for a simpler
interface whenever transaction overhead is not critical.
The main memory area is organized as a linear,
byte-addressable space of 32 Kbytes. Of this, the first
24-Kbyte area (0000h through 5FFFh) is implemented
as the SRAM buffer. The buffer is accessed by the
device using several SFRs as memory pointers and
virtual data window registers, as described in
Section 3.5.5 “Indirect SRAM Buffer Access”.
Addresses in the main memory area, between 7800h
and 7C4Fh, are mapped to the memory for the crypto-
graphic data modules. These addresses are not
directly accessible through the SPI interface; they can
only be accessed through the DMA.
The PHY SFRs are the final memory space. This is a
linear, word-addressable memory space of 32 words.
This area is only accessible by the MIIM interface (see
Section 3.3 “PHY Special Function Registers” for
more details).
00h
1Fh
Main Area
SPI INTERFACE MAP
Cryptographic Data
(DMA access only)
Unimplemented
Unimplemented
SRAM Buffer
Pointers
DS39935C-page 17
7C4Fh
5FFFh
7FFFh
0000h
7800h