PCX107AVZFU100LC E2V, PCX107AVZFU100LC Datasheet - Page 9

• Manufacturer Part Number: PCX107AVZFU100LC
• Description: IC PCI BRIDGE MEM CTRLR 503PBGA
• Manufacturer: E2V

Specifications of PCX107AVZFU100LC

• Controller Type: PCI Controller
• Interface: PCI
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 503-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -

Notes:
2137D–HIREL–08/05
1. This pin has an internal pull-up resistor which is enabled only when the PC107A is in the reset state. The value of the inter-
2. This pin is a reset configuration pin.
3. MDL[0] is a reset configuration pin and has an internal pull-up resistor which is enabled only when the MPC107 is in the
4. Multi-pin signals such as AD[0–31] or DL[0–31] have their physical package pin numbers listed in order corresponding to the
5. SDMA[10–1] are reset configuration pins and have internal pull-up resistors which are enabled only when the MPC107 is in
6. Recommend a weak pull-up resistor (2 kΩ– 10 kΩ) be placed on this PCI control pin to LV
7. V
8. Recommend a weak pull-up resistor (2 kΩ – 10 kΩ) be placed on this pin to OV
9. Recommend a weak pull-up resistor (2 kΩ – 10 kΩ) be placed on this pin to GV
10. This pin has an internal pull-up resistor; the value of the internal pull-up resistor is not guaranteed, but is sufficient to prevent
11. This pin is affected by programmable PCI_HOLD_DEL parameter, see
12. This pin is an open drain signal.
13. This pin is a sustained tri-state pin as defined by the PCI Local Bus Specification.
14. See “Connection Recommendations” on
15. A weak pull-up resistor is recommend (2 kΩ – 10 kΩ) to be placed on this pin to BV
16. If BV
nal pull-up resistor is not guaranteed, but is sufficient to ensure that a logic "1" is read into configuration bits during reset.
reset state.The value of the internal pull-up resistor is not guaranteed, but is sufficient to insure that a logic '1' is read into
configuration bits during reset.
signal names. Ex: AD0 is on pin D21, AD1 is on pin D23,... AD31 is on pin N23.
the reset state.The values of the internal pull-up resistors is not guaranteed, but are sufficient to ensure that logic "1"s are
read into the configuration bits during reset.
unused inputs from floating.
±
IH
5%; this can typically be accomplished with a two resistor voltage divider circuit since the signal is an output only signal.
and V
DD
= 2.5V
IL
for these signals are the same as the PCI V
±
5%, this microprocessor interface pin needs to be DC voltage level shifted from OV
page 44
for additional information on this pin.
IH
and V
IL
entries in
”PCI Signal Output Hold Timing” on page
Table
DD
DD
7-1, “DC Electrical Specifications.”
.
.
DD
.
DD
.
DD
(3.3
PC107A
±
0.3V) to 2.5V
30.”
9