PCX107AVZFU100LC E2V, PCX107AVZFU100LC Datasheet - Page 45

• Manufacturer Part Number: PCX107AVZFU100LC
• Description: IC PCI BRIDGE MEM CTRLR 503PBGA
• Manufacturer: E2V

Specifications of PCX107AVZFU100LC

• Controller Type: PCI Controller
• Interface: PCI
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 503-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -

10.5
2137D–HIREL–08/05
Pull-up/Pull-down Resistor Requirements
The data bus input receivers are normally turned off when no read operation is in progress;
therefore, they do not require pull-up resistors on the bus. The processor data bus signals are:
DH[0
and PAR/AR[0
If the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits
(DL[0
zeros when they would otherwise normally be driven. For this mode, these pins do not require
pull-up resistors, and should be left unconnected by the system to minimize possible output
switching.
It is recommended that ARTRY, TA, and TS have weak pull-up resistors (2 kΩ
nected to BV
It is recommended that MTP[1
nected to GV
It is recommended that the following signals be pulled up to OV
kΩ
It is recommended that the following PCI control signals be pulled up to LV
resistors (2 kΩ
INTA. The resistor values may need to be adjusted stronger to reduce induced noise on specific
board designs.
The following pins have internal pull-up resistors enabled at all times: REQ[06
TMS, and TRST, BR1, HRESET_CPU, MCP, QACK, SRESET, TEST and TRIG_OUT. See
Table 2-1, “PC107A Pinout Listing,” on page 5
The following pins have internal pull-up resistors enabled only while device is in the reset state:
MDL0, FOE, RCS0, SDRAS, SDCAS, CKE, SDBAO, and SDMA[10
“PC107A Pinout Listing,” on page 5
The following pins are reset configuration pins: MDL0, FOE, RCS0, SDBAO, SDMA[10
PLL_CFG[0
Any other unused active low input pins should be tied to a logic one level via weak pull-up resis-
tors (2 kΩ
active high input pins should be tied to GND via weak pull-down resistors (2 kΩ
–
–
10 kΩ): SDA, SCL, TEST1, and FTP[3
–
31], DL[0
31], DP[4
–
–
DD
3]. These pins are sampled during reset to configure the device.
10 kΩ) to the appropriate power supply listed in
DD
–
.
.
–
7].
–
–
31], and PAR[0
7], MDL[0
10 kΩ): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP, TRDY and
–
31], and PAR[4
–
–
2] and TEST2 have weak pull-up resistor (2 kΩ
7]. The memory data bus signals are: MDH[0
for more information.
–
–
7]) will be disabled, and their outputs will drive logic
3].
for more information.
Table 5-2 on page
DD
with weak pull-up resistors (2
–
DD
1]. See
with weak pull-up
–
–
31], MDL[0
PC107A
–
10 kΩ).
–
–
4], TCK, TDI,
10 kΩ) con-
10 kΩ) con-
12. Unused
Table 2-1,
–
1], and
–
31],
45