PCX107AVZFU100LC E2V, PCX107AVZFU100LC Datasheet - Page 43

• Manufacturer Part Number: PCX107AVZFU100LC
• Description: IC PCI BRIDGE MEM CTRLR 503PBGA
• Manufacturer: E2V

Specifications of PCX107AVZFU100LC

• Controller Type: PCI Controller
• Interface: PCI
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 503-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -

10. System Design Information
10.1
10.2
2137D–HIREL–08/05
PLL Power Supply Filtering
Power Supply Voltage Sequencing
The AV
eral logic/memory bus PLL and the SDRAM clock delay-locked loop (DLL), respectively. To
ensure stability of the internal clocks, the power supplied to the AV
should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency range of the PLLs.
A separate circuit similar to the one shown in
minimum effective series inductance (ESL) is recommended for each of the AV
power signal pins. Consistent with the recommendations of Dr. Howard Johnson in High Speed
Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of
equal value are recommended over using multiple values.
The circuits should be placed as close as possible to the respective input signal pins to minimize
noise coupled from nearby circuits. Routing directly as possible from the capacitors to the input
signal pins with minimal inductance of vias is important but proportionately less critical for the
LAV
Figure 10-1. PLL Power Supply Filter Circuit
The notes in
the sequencing of the external bus voltages and internal voltages of the PC107A. These cau-
tions are necessary for the long term reliability of the part. If they are violated, the electrostatic
discharge (ESD) protection diodes will be forward biased and excessive current can flow
through these diodes.
power sources (voltage regulators and/or power supplies) are connected as shown in
2. The voltage regulator delay shown in
are all applied to the target board at the same time. The ramping voltage sequence shows a sce-
nario in which the V
plane and thus V
If the system power supply design does not control the voltage sequencing, the circuit of
10-2
maximum potential difference between the 3.3 bus and internal voltages on power-up and the
1N5820 Schottky diodes regulate the maximum potential difference on power-down.
DD
can be added to meet these requirements. The MUR420 diodes of
pin.
DD
and LAV
Vdd
Table 5-2 on page 12
DD
DD
/AV
DD
power signals are provided on the PC107A to provide power to the periph-
/AV
DD
Figure 5-1
10Ω
/LAV
DD
/LAV
DD
ramps at a faster rate than OV
DD
2.2 µF
power plane is not loaded as much as the OV
shows a typical ramping voltage sequence where the DC
contain cautions illustrated in
Figure 5-1
GND
Figure 10-1
can be zero if the various DC voltage levels
2.2 µF
Low ESL surface mount capacitors
using surface mount capacitors with
DD
AVdd or LAVdd
/GV
Figure 5-1 on page 13
DD
DD
.
and LAV
Figure 10-2
DD
PC107A
DD
DD
input signals
/GV
and LAV
control the
Figure 10-
DD
Figure
power
about
43
DD