PCX107AVZFU100LC E2V, PCX107AVZFU100LC Datasheet - Page 34

• Manufacturer Part Number: PCX107AVZFU100LC
• Description: IC PCI BRIDGE MEM CTRLR 503PBGA
• Manufacturer: E2V

Specifications of PCX107AVZFU100LC

• Controller Type: PCI Controller
• Interface: PCI
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 503-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -

Table 7-10.
Notes:
Figure 7-10.
34
Num
1
2
3
4
5
6
7
8
9
1. Units for these specifications are in SDRAM_CLK/CPU_CLK units.
2. The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in the Frequency
3. Since SCL and SDA are open-drain type outputs, which the PC107A can only drive low, the time required for SCL or SDA to
4. Specified at a nominal 50 pF load.
5. D
PC107A
Characteristics
Start condition hold time
Clock low period
SCL/SDA rise time (from 0.5V to 2.4V)
Data hold time
SCL/SDA fall time (from 2.4V to 0.5V)
Clock high time
Data setup time (PC107A as a master only)
Start condition setup time (for repeated start
condition only)
Stop condition setup time
Divider Register I2CFDR. Therefore, the noted timings in the above table are all relative to qualified signals. The qualified
SCL and SDA are delayed signals from what is seen in real time on the two-wire interface bus. The qualified SCL, SDA sig-
nals are delayed by the SDRAM_CLK/CPU_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK/CPU_CLK clock. The
resulting delay value is added to the value in the table (where this note is referenced). See
reach a high level depends on external signal capacitance and pull-up resistor values.
quency Divider Selections table. FDR[x] refers to the Frequency Divider Register I2CFDR bit x. N is equal to a variable
number that would make the result of the divide (Data Hold Time value) equal to a number less than 16. M is equal to a vari-
able number that would make the result of the divide (Data Hold Time value) equal to a number less than 9.
FDR
Two-wire Interface
Two-wire Interface
is the decimal divider number indexed by FDR[5:0] value. Refer to the two-wire Interface chapter’s Serial Bit Clock Fre-
SDA
SCL
Table 7-10
At recommended operating conditions (see
LV
VM
DD
1
= 3.3
Output AC Timing Specifications
Timing Diagram II
±
provides the
0.3V
2
two-wire interface
VM
(D
D
(FDR[5] == 0)
FDR
(FDR[5] == 1)
FDR
6
4
4({FDR[5],FDR[1]} == b’10) -
3({FDR[5],FDR[1]} == b’11) -
2({FDR[5],FDR[1]} == b’00) -
1({FDR[5],FDR[1]} == b’01))
8.0 + (16
+ (Output start condition hold
/ 2) - (Output data hold time)
D
D
×
output AC timing specifications for the PC107A.
FDR
FDR
time)
Min
×
4.0
2
×
–
–
FDR[4:2]
(D
(D
Table 5-2 on page
/ 2
/ 2
FDR
FDR
/16) / 2N +
)
/16) / 2M
×
(5 -
12) with GV
Max
< 5
–
–
–
–
–
–
–
–
Figure 7-11 on page
CLKs
CLKs
CLKs
CLKs
CLKs
CLKs
CLKs
DD
Unit
mS
ns
= 3.3V
2137D–HIREL–08/05
35.
±
Notes
(1)(2)(5)
(1)(2)(5)
(1)(2)(5)
(1)(2)(5)
(1)(2)(5)
(1)(5)
(1)(2)
5% and
(3)
(4)