PCX107AVZFU100LC E2V, PCX107AVZFU100LC Datasheet - Page 44

• Manufacturer Part Number: PCX107AVZFU100LC
• Description: IC PCI BRIDGE MEM CTRLR 503PBGA
• Manufacturer: E2V

Specifications of PCX107AVZFU100LC

• Controller Type: PCI Controller
• Interface: PCI
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 503-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -

10.3
10.4
44
Decoupling Recommendations
Connection Recommendations
PC107A
Figure 10-2. Example Voltage Sequencing Circuits
Due to the PC107A’s dynamic power management feature, large address and data buses, and
high operating frequencies, the PC107A can generate transient power surges and high fre-
quency noise in its power supply, especially while driving large capacitive loads. This noise must
be prevented from reaching other components in the PC107A system, and the PC107A itself
requires a clean, tightly regulated source of power. Therefore, it is recommended that the sys-
tem designer place at least one decoupling capacitor at each V
the PC107A. It is also recommended that these decoupling capacitors receive their power from
separate V
inductance. These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount
technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603,
oriented such that connections are made along the length of the part.
In addition, it is recommended that there be several bulk storage capacitors distributed around
the PCB, feeding the V
smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resis-
tance) rating to ensure the quick response time necessary. They should also be connected to
the power and ground planes through two vias to minimize inductance. Suggested bulk capaci-
tors-100
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropri-
ate signal level. Unused active low inputs should be tied to OV
should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V
GND pins of the PC107A.
The PCI_SYNC_OUT signal is intended to be routed halfway out to the PCI devices and then
returned to the PCI_SYNC_IN input of the PC107A.
The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM devices
and then returned to the SDRAM_SYNC_IN input of the PC107A. The trace length may be used
to skew or adjust the timing window as needed. See Freescale application note "AN1794/D" for
more information on this topic.
The TRST signal must be asserted during reset to ensure proper initialization and operation of
the PC107A. It is recommended that the TRST signal be connected to the system HRESET sig-
nal or pulled down with a 100Ω - 1 kΩ resistor.
+ 5V
Source
–
330 µF (AVX TPS tantalum or Sanyo OSCON).
DD
, OV
DD
+ 3.3V
Source
+ 2.5V
Source
, GV
DD
DD
, OV
, and GND power planes in the PCB, utilizing short traces to minimize
DD
, GV
5V
3.3V
2.5V
DD
, BV
3.3V
DD
, and LV
DD
MUR420
planes, to enable quick recharging of the
IN5820
DD
DD
, OV
DD
, OV
. Unused active high inputs
IN5820
MUR420
DD
DD
, GV
, GV
DD
DD
, LV
, and LV
2137D–HIREL–08/05
DD
, BV
2.5V
DD
DD
pin of
, and