PCX107AVZFU100LC E2V, PCX107AVZFU100LC Datasheet - Page 39

• Manufacturer Part Number: PCX107AVZFU100LC
• Description: IC PCI BRIDGE MEM CTRLR 503PBGA
• Manufacturer: E2V

Specifications of PCX107AVZFU100LC

• Controller Type: PCI Controller
• Interface: PCI
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 503-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -

8. Preparation for Delivery
8.1
8.2
8.3
8.4
Table 8-1.
2137D–HIREL–08/05
Ref
A
C
D
1
2
3
5
8
9
F
Packaging
Certificate of Compliance
Handling
Choice of Clock Relationships
PLL_CFG
[0–3]
0001
0010
0011
0101
1000
1001
1010
1100
1101
1111
PC107A Microprocessor PLL Configuration
(2)
Microcircuits are prepared for delivery in accordance with internal standards.
Atmel offers a certificate of compliance with each shipment of parts, affirming the products are in
compliance either with internal specifications and guaranteeing the parameters not tested at
temperature extremes for the entire temperature range.
MOS devices must be handled with certain precautions to avoid damage due to accumulation of
static charge. Input protection devices have been designed in the chip to minimize the effect of
this static buildup. However, the following handling practices are recommended:
The PC107A’s internal PLL is configured by the PLL_CFG[0
PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set the Core/Memory/Proces-
sor PLL (VCO) frequency of operation for the PCI-to-Core/Memory/Processor frequency
multiplying, if any. All valid PLL configurations for the PC107A are shown in
PCI_SYNC_IN
Range (MHz)
• Devices should be handled on benches with conductive and grounded surfaces
• Ground test equipment, tools and operator
• Do not handle devices by the leads
• Store devices in conductive foam or carriers
• Avoid use of plastic, rubber or silk in MOS areas
• Maintain relative humidity above 50% if practical
13
Clock off
13
25
25
17
34
20
50
(5)
(4)
(5)
(5)
(5)
(5)
(5)
(5)
– 16
–
– 33
– 33
– 22
– 44
16
– 26
– 66
(7)
66 MHz Part
(3)
(4)
Bypass
Core/Mem/CPU
Range (MHz)
Not Usable
25 – 33
26 – 34
50 – 66
51 – 66
51 – 66
50 – 65
50 – 66
52–64
PCI_SYNC_IN
Range (MHz)
25
13
Clock off
13
25
17
33
20
50
(5)
(5)
(4)
(5)
(5)
(5)
(5)
(5)
– 50
– 25
–
– 50
– 33
– 66
– 40
– 66
25
100 MHz Part
(7)
(4)
(4)
(3)
Bypass
Core/Mem/CPU
Range (MHz)
Not Usable
50 – 100
50 – 100
50 – 100
50 – 100
25 – 50
26 – 50
52–100
50 – 66
–
3] signals. For a given
PCI: Core
Bypass
Ratio
1.5
2.5
Off
1
2
2
3
4
1
Table
PC107A
8-1.
Multiplier
Bypass
VCO
Off
4
4
2
2
2
2
2
2
39