PCX107AVZFU100LC E2V, PCX107AVZFU100LC Datasheet - Page 30

• Manufacturer Part Number: PCX107AVZFU100LC
• Description: IC PCI BRIDGE MEM CTRLR 503PBGA
• Manufacturer: E2V

Specifications of PCX107AVZFU100LC

• Controller Type: PCI Controller
• Interface: PCI
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 503-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -

7.2.5
Table 7-7.
30
6 – 4
Bit
PCI_HOLD_DEL
PC107A
PCI Signal Output Hold Timing
Name
Power Management Configuration Register 2-0x72
In order to meet minimum output hold specifications relative to PCI_SYNC_IN for both 33 MHz
and 66 MHz PCI systems, the PC107A has a programmable output hold delay for PCI signals.
The initial value of the output hold delay is determined by the values on the SDMA4 and SDMA3
reset configuration signals. Further output hold delay values are available by programming the
PCI_HOLD_DEL value of the PMCR2 configuration register.
Table 7-7
Reset value
xx0
describes the bit values for the PCI_HOLD_DEL values in PMCR2.
PCI output hold delay values relative to PCI_SYNC_IN. The initial values of bits 6 and 5
are determined by the reset configuration pins
these two pins have internal pull-up resistors, the default value after reset is 0b110.
While the minimum hold times are guaranteed at shown values, changes in the actual
hold time can be made by incrementing or decrementing the value in these bit fields of
this register via software or hardware configuration. The increment is in approximately
400 picosecond steps. Lowering the value in the three bit field decreases the amount of
output hold available.
000 66 MHz PCI. Pull-down
001
010
011
100 33 MHz PCI. This setting guarantees the minimum output hold,
101
110 (Default if reset configuration pins left unconnected)
111
value resistor. This setting guarantees the minimum output hold,
item 13a, and the maximum output valid, item 12a, times as specified in
Figure 7-6
item 13a, and the maximum output valid, item 12a, times as specified in
Figure 7-6
are met for a 66 MHz PCI system. See
are met for a 33 MHz PCI system. See
SDMA4
Description
configuration pin with a 2 kΩ or less
SDMA4
Figure 7-9 on page
Figure 7-9 on page
and
SDMA3
, respectively. As
2137D–HIREL–08/05
31.
31.