PCX107AVZFU100LC E2V, PCX107AVZFU100LC Datasheet - Page 32

• Manufacturer Part Number: PCX107AVZFU100LC
• Description: IC PCI BRIDGE MEM CTRLR 503PBGA
• Manufacturer: E2V

Specifications of PCX107AVZFU100LC

• Controller Type: PCI Controller
• Interface: PCI
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 503-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -

7.2.6
Table 7-8.
Notes:
32
Num
1
2
3
4
5
6
7
8
9
1. Units for these specifications are in SDRAM_CLK/CPU_CLK units.
2. The actual values depend on the setting of the Digital Filter Frequency Sampling Rate (DFFSR) bits in the Frequency
3. Timing is relative to the Sampling Clock (not SCL).
4. FDR[x] refers to the Frequency Divider Register I2CFDR bit x.
5. Input clock low and high periods in combination with the FDR value in the Frequency Divider Register (I2CFDR) determine
Characteristics
Start condition hold time
Clock low period
(The time before the PC107A will drive SCL low as a
transmitting slave after detecting SCL low as driven by an
external master)
SCL/SDA rise time (from 0.5V to 2.4V)
Data hold time
SCL/SDA fall time (from 2.4V to 0.5V)
Clock high period
(Time needed to either receive a data bit or generate a
START or STOP)
Data setup time
Start condition setup time (for repeated start condition
only)
Stop condition setup time
PC107A
Two-wire Interface AC Timing Specifications
Divider Register two-wire interface FDR. Therefore, the noted timings in the above table are all relative to qualified signals.
The qualified SCL and SDA are delayed signals from what is seen in real time on the two-wire interface bus. The qualified
SCL, SDA signals are delayed by the SDRAM_CLK/CPU_CLK clock times DFFSR times 2 plus 1 SDRAM_CLK/CPU_CLK
clock. The resulting delay value is added to the value in the table (where this note is referenced). See
35.
the maximum two-wire interface input frequency. See
Two-wire Interface Input AC Timing Specifications
Table 7-8
At recommended operating conditions (see
provides the two-wire interface input AC timing specifications for the PC107A.
Figure 7-11 on page
4({FDR[5],FDR[1]} == b’10) -
3({FDR[5],FDR[1]} == b’11) -
2({FDR[5],FDR[1]} == b’00) -
1({FDR[5],FDR[1]} == b’01))
8.0 + (16
Table 5-2 on page
×
Min
4.0
5.0
3.0
4.0
4.0
2
–
0
–
FDR[4:2]
35.
)
×
(5 -
12) with
Max
–
–
1
–
1
–
–
–
–
LV
DD
Figure 7-11 on page
= 3.3
CLKs
CLKs
CLKs
CLKs
CLKs
Unit
mS
ms
ns
ns
2137D–HIREL–08/05
±
0.3V
(1)(2)(4)(5)
Notes
(1)(2)(5)
(1)(2)
(1)(2)
(1)(2)
(2)
(3)