ISP1161ABD-S ST-Ericsson Inc, ISP1161ABD-S Datasheet - Page 14

• Manufacturer Part Number: ISP1161ABD-S
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD-S

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
9397 750 13962
Product data
8.3.1 I/O port addressing
8.3 Control register access by PIO mode
Figure 9
ISP1161A. The ISP1161A provides two DMA channels:
The EOT signal is an external end-of-transfer signal used to terminate the DMA
transfer. Some microprocessors may not have this signal. In this case, the ISP1161A
provides an internal EOT signal to terminate the DMA transfer as well. Setting the
HcDMAConfiguration register (21H - read, A1H - write) enables the ISP1161A HC
internal DMA counter for DMA transfer. When the DMA counter reaches the value set
in the HcTransferCounter register (22H - read, A2H - write), an internal EOT signal
will be generated to terminate the DMA transfer.
Table 3
address should include the chip select signal CS and the address lines A1 and A0.
However, the direction of the access of the I/O ports is controlled by the RD and WR
signals. When RD is LOW, the microprocessor reads data from the ISP1161A data
port. When WR is LOW, the microprocessor writes a command to the command port,
or writes data to the data port.
Table 3:
•
•
Fig 9. DMA interface between a microprocessor and an ISP1161A.
Port
DMA channel 1 (controlled by DREQ1, DACK1 signals) is for the DMA transfer
between a microprocessor’s system memory and ISP1161A HC internal FIFO
buffer RAM
DMA channel 2 (controlled by DREQ2, DACK2 signals) is for the DMA transfer
between a microprocessor system memory and the ISP1161A DC internal FIFO
buffer RAM.
0
1
2
3
shows the ISP1161A I/O port addressing. Complete decoding of the I/O port
Pin CS
shows the DMA interface between a microprocessor system and the
LOW
LOW
LOW
LOW
I/O port addressing
Rev. 03 — 23 December 2004
Pin A1
HIGH
HIGH
PROCESSOR
LOW
LOW
MICRO-
Full-speed USB single-chip host and device controller
Pin A0
HIGH
HIGH
LOW
LOW
DREQ1
DREQ2
D [ 15:0 ]
DACK1
DACK2
EOT
WR
RD
Access
µP bus I/F
R/W
R/W
W
W
Data bus width
D [ 15:0 ]
RD
WR
DACK1
DREQ1
DACK2
DREQ2
EOT
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
16 bits
16 bits
16 bits
16 bits
ISP1161A
004aaa087
ISP1161A
HC command port
DC command port
HC data port
DC data port
Description
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