ISP1161ABD-S ST-Ericsson Inc, ISP1161ABD-S Datasheet - Page 95

• Manufacturer Part Number: ISP1161ABD-S
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD-S

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
Table 80:
[1]
Table 82:
9397 750 13962
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Unchanged by a bus reset.
DcMode register: bit allocation
DcHardwareConfiguration register: bit allocation
reserved
DMAWD
R/W
R/W
0
15
7
0
[1]
13.1.4 DcHardwareConfiguration register (R/W: BBH/BAH)
reserved
Table 81:
This command is used to access the DcHardwareConfiguration register, which
consists of 2 bytes. The first (lower) byte contains the device configuration and
control values, the second (upper) byte holds the clock control bits and the clock
division factor. The bit allocation is given in
of the programmed bit values.
The DcHardwareConfiguration register controls the connection to the USB bus, clock
activity and power supply during ‘suspend’ state, output clock frequency, DMA
operating mode and pin configurations (polarity, signalling mode).
Code (Hex): BA/BB — write/read DcHardwareConfiguration register
Transaction — write/read 1 word
EXTPUL
Bit
7
6
5
4
3
2
1
0
R/W
R/W
14
6
0
0
DcMode register: bit description
Symbol
DMAWD
-
GOSUSP
-
INTENA
DBGMOD
-
SOFTCT
GOSUSP
NOLAZY
R/W
R/W
13
5
0
1
Rev. 03 — 23 December 2004
CLKRUN
reserved
Description
Logic 1 selects 16-bit DMA bus width (bus configuration
modes 0 and 2). Logic 0 selects 8-bit DMA bus width. Bus reset
value: unchanged.
reserved
Writing logic 1 followed by logic 0 will activate ‘suspend’ mode.
reserved
Logic 1 enables all DC interrupts. Bus reset value: unchanged;
for details, see
Logic 1 enables debug mode, where all NAKs and errors will
generate an interrupt. Logic 0 selects normal operation, where
interrupts are generated on every ACK (bulk endpoints) or after
every data transfer (isochronous endpoints).
Bus reset value: unchanged.
reserved
Logic 1 enables SoftConnect (see
ignored if EXTPUL = 1 in the DcHardwareConfiguration register
(see
Full-speed USB single-chip host and device controller
R/W
R/W
12
4
0
0
Table
82). Bus reset value: unchanged.
INTENA
R/W
R/W
0
Section
11
3
0
[1]
Table
8.6.3.
DBGMOD
82. A bus reset will not change any
R/W
R/W
0
10
2
0
[1]
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
CLKDIV[3:0]
Section
reserved
ISP1161A
R/W
R/W
0
7.5). This bit is
1
9
1
[1]
SOFTCT
R/W
R/W
94 of 134
0
0
8
1
[1]