ISP1161ABD-S ST-Ericsson Inc, ISP1161ABD-S Datasheet - Page 68

• Manufacturer Part Number: ISP1161ABD-S
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD-S

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
Table 40:
9397 750 13962
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcTransferCounter register: bit allocation
R/W
R/W
15
0
7
0
10.4.3 HcTransferCounter register (R/W: 22H/A2H)
Table 39:
This register holds the number of bytes of a PIO or DMA transfer. For a PIO transfer,
the number of bytes being read or written to the Isochronous Transfer List (ITL) or
Acknowledged Transfer List (ATL) buffer RAM must be written into this register. For a
DMA transfer, the number of bytes must be written into this register as well. However,
for this counter to be read into the DMA counter, the HCD must set bit 2 of the
HcDMAConfiguration register. The counter value for ATL must not be greater than
1000H, and for ITL it must not be greater than 800H. When the byte count of the data
transfer reaches this value, the HC will generate an internal EOT signal to set bit 2
(AllEOTInterrupt) of the HcµPInterrupt register, and also update the HcBufferStatus
register.
Code (Hex): 22 — read
Code (Hex): A2 — write
Table 41:
Bit
2
1
0
Bit
15 to 0
R/W
R/W
14
0
6
0
Symbol
DMACounter
Select
ITL_ATL_
DataSelect
DMARead
WriteSelect
HcDMAConfiguration register: bit description
HcTransferCounter register: bit description
Symbol
Counter
value
R/W
R/W
13
0
5
0
Rev. 03 — 23 December 2004
Description
0 — DMA counter not used. External EOT must be used
1 — Enables the DMA counter for DMA transfer.
HcTransferCounter register must be filled with non-zero values for
DREQ1 to be raised after bit DMA Enable is set
0 — ITL buffer RAM selected for ITL data
1 — ATL buffer RAM selected for ATL data
0 — read from the HC FIFO buffer RAM
1 — write to the HC FIFO buffer RAM
Description
The number of data bytes to be read to or written from RAM
Full-speed USB single-chip host and device controller
R/W
R/W
12
0
4
0
Counter value
Counter value
R/W
R/W
11
0
3
0
R/W
R/W
10
0
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
…continued
ISP1161A
R/W
R/W
9
0
1
0
R/W
R/W
67 of 134
8
0
0
0