ISP1161ABD-S ST-Ericsson Inc, ISP1161ABD-S Datasheet - Page 21

• Manufacturer Part Number: ISP1161ABD-S
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD-S

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
9397 750 13962
Product data
Fig 20. HC interrupt logic.
HcInterruptEnable
HcInterruptStatus
register
register
RHSC
RHSC
FNO
FNO
MIE
UE
RD
SO
UE
RD
SO
SF
SF
There are two groups of interrupts represented by group 1 and group 2 in
A pair of registers control each group.
Group 2 contains six possible interrupt events (recorded in the HcInterruptStatus
register). On occurrence of any of these events, the corresponding bit would be set to
logic 1; and if the corresponding bit in the HcInterruptEnable register is also logic 1,
the 6-input OR gate would output logic 1. This output is ANDed with the value of MIE
(bit 31 of HcInterruptEnable). Logic 1 at the AND gate will cause bit OPR in the
HcµPInterrupt register to be set to logic 1.
Group 1 contains six possible interrupt events, one of which is the output of group 2
interrupt sources. The HcµPInterrupt and HcµPInterruptEnable registers work in the
same way as the HcInterruptStatus and HcInterruptEnable registers in the interrupt
group 2. The output from the 6-input OR gate is connected to a latch, which is
controlled by InterruptPinEnable (bit 0 of the HcHardwareConfiguration register).
In the event in which the software wishes to temporarily disable the interrupt output of
the ISP1161A Host Controller, the following procedure should be followed:
1. Make sure that bit InterruptPinEnable in the HcHardwareConfiguration register is
2. Clear all bits in the HcµPInterrupt register.
3. Set bit InterruptPinEnable to logic 0.
set to logic 1.
group 2
OR
Rev. 03 — 23 December 2004
INT1
HcµPInterrupt
register
Full-speed USB single-chip host and device controller
LATCH
OR
LE
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
HcµPInterruptEnable
HcHardwareConfiguration
register
ISP1161A
InterruptPinEnable
register
Figure
MGT945
20 of 134
20.