ISP1161ABD-S ST-Ericsson Inc, ISP1161ABD-S Datasheet - Page 93

• Manufacturer Part Number: ISP1161ABD-S
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD-S

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
Table 75:
[1]
[2]
[3]
[4]
[5]
[6]
Table 76:
9397 750 13962
Product data
Name
Read Endpoint n Error Code
(n = 1 to 14)
Unlock Device
Write/Read DcScratch register
Read Frame Number
Read Chip ID
Read DcInterrupt register
Bit
Symbol
Reset
Access
With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1) DIV 2.
Validating an OUT endpoint buffer causes unpredictable behavior of ISP1161A’s DC.
Clearing an IN endpoint buffer causes unpredictable behavior of ISP1161A’s DC.
Reads a copy of the DcStatus register: executing this command does not clear any status bits or interrupt bits.
When accessing an 8-bit register in 16-bit mode, the upper byte is invalid.
During isochronous transfer in 16-bit mode, because N ≤ 1023, the firmware must take care of the upper byte.
DC command and register summary
DcEndpointConfiguration register: bit allocation
FIFOEN
R/W
7
0
13.1.1 DcEndpointConfiguration register (R/W: 30H–3FH/20H–2FH)
13.1 Initialization commands
Initialization commands are used during the enumeration process of the USB
network. These commands are used to configure and enable the embedded
endpoints. They also serve to set the USB assigned address of ISP1161A’s DC and
to perform a device reset.
This command is used to access the DcEndpointConfiguration register (ECR) of the
target endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction
(OUT/IN), FIFO size and buffering scheme. It also enables the endpoint FIFO. The
register bit allocation is shown in
The allocation of FIFO memory only takes place after all 16 endpoints have been
configured in sequence (from endpoint 0 OUT to endpoint 14). Although the control
endpoints have fixed configurations, they must be included in the initialization
sequence and be configured with their default values (see
allocation starts when endpoint 14 has been configured.
Remark: If any change is made to an endpoint configuration which affects the
allocated memory (size, enable/disable), the FIFO memory contents of all endpoints
becomes invalid. Therefore, all valid data must be removed from enabled endpoints
before changing the configuration.
Code (Hex): 20 to 2F — write (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 30 to 3F — read (control OUT, control IN, endpoint 1 to 14)
Transaction — write/read 1 word
EPDIR
R/W
6
0
Destination
DcErrorCode register
endpoint 1 to 14
all registers with write access
DcScratch register
DcFrameNumber register
DcChipID register
DcInterrupt register
DBLBUF
R/W
5
0
Rev. 03 — 23 December 2004
…continued
FFOISO
Full-speed USB single-chip host and device controller
R/W
4
0
Table
76. A bus reset will disable all endpoints.
R/W
3
0
Code (Hex)
A2 to AF
B0
B2/B3
B4
B5
C0
R/W
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
FFOSZ[3:0]
Table
Transaction
read 1 word
write 1 word
write/read 1 word
read 1 word
read 1 word
read 2 words
66). Automatic FIFO
ISP1161A
R/W
1
0
[1]
[5]
R/W
92 of 134
0
0