ISP1161ABD-S ST-Ericsson Inc, ISP1161ABD-S Datasheet - Page 97

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ISP1161ABD-S

Manufacturer Part Number
ISP1161ABD-S
Description
IC USB HOST CTRL FULL-SPD 64LQFP
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1161ABD-S

Controller Type
USB 2.0 Controller
Interface
Parallel
Voltage - Supply
3.3V, 5V
Current - Supply
47mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISP1161ABD-S
Manufacturer:
ST-Ericsson Inc
Quantity:
10 000
Philips Semiconductors
Table 84:
9397 750 13962
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DcInterruptEnable register: bit allocation
IEP14
R/W
R/W
31
23
0
0
13.1.5 DcInterruptEnable register (R/W: C3H/C2H)
This command is used to individually enable or disable interrupts from all endpoints,
as well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT,
suspend, resume, reset). That is, if an interrupt event occurs while the interrupt is not
enabled, nothing will be seen on the interrupt pin. Even if you then enable the
interrupt during the interrupt event, there will still be no interrupt seen on the interrupt
pin, see
The DcInterrupt register will not register any interrupt, if it is not already enabled
using the DcInterruptEnable register. The DcInterruptEnable register is not an
Interrupt Mask register.
A bus reset will not change any of the programmed bit values.
The command accesses the DcInterruptEnable register, which consists of 4 bytes.
The bit allocation is given in
Remark: For details on interrupt control, see
Code (Hex): C2/C3 — write/read DcInterruptEnable register
Transaction — write/read 2 words
IEP13
Fig 42. Interrupt pin waveform.
R/W
R/W
30
22
0
0
Pin INT2: HIGH = de-assert; LOW = assert; INTENA = 1.
Figure
IEP12
R/W
R/W
29
21
42.
0
0
Rev. 03 — 23 December 2004
INT2 pin
DcInterruptEnable
disabled
register
interrupt
occurs
event
IEP11
Full-speed USB single-chip host and device controller
R/W
R/W
28
20
Table
0
0
reserved
DcInterruptEnable
84.
enabled
register
IEP10
R/W
R/W
27
19
0
0
Section
interrupt
occurs
event
IEP9
R/W
R/W
26
18
interrupt is cleared
0
0
8.6.3.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
004aaa197
IEP8
ISP1161A
R/W
R/W
25
17
0
0
IEP7
R/W
R/W
96 of 134
24
16
0
0

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