ISP1161ABD-S ST-Ericsson Inc, ISP1161ABD-S Datasheet - Page 91

• Manufacturer Part Number: ISP1161ABD-S
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD-S

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
13. DC commands and registers
Table 75:
9397 750 13962
Product data
Name
Initialization commands
Write Control OUT Configuration
Write Control IN Configuration
Write Endpoint n Configuration
(n = 1 to 14)
Read Control OUT Configuration
Read Control IN Configuration
Read Endpoint n Configuration
(n = 1 to 14)
Write/Read Device Address
Write/Read DcMode register
Write/Read Hardware Configuration DcHardwareConfiguration register
Write/Read DcInterruptEnable
register
Write/Read DMA Configuration
Write/Read DMA Counter
Reset Device
DC command and register summary
The functions and registers of ISP1161A’s DC are accessed via commands, which
consist of a command code followed by optional data bytes (read or write action). An
overview of the available commands and registers is given in
A complete access consists of two phases:
As the ISP1161A DC’s data bus is 16 bits wide:
•
•
•
1. Command phase: when address bit A0 = 1, the DC interprets the data on the
2. Data phase (optional): when address bit A0 = 0, the DC transfers the data on
The upper byte (bits D15 to D8) in command phase, or the undefined byte in data
phase and is ignored.
The access of registers is word-aligned: byte access is not allowed.
If the packet length is odd, the upper byte of the last word in an IN endpoint buffer
is not transmitted to the host. When reading from an OUT endpoint buffer, the
upper byte of the last word must be ignored by the firmware. The packet length is
stored in the first 2 bytes of the endpoint buffer.
lower byte of the bus (bits D7 to D0) as a command code. Commands without a
data phase are executed immediately.
the bus to or from a register or endpoint FIFO. Multi-byte registers are accessed
least significant byte/word first.
Destination
DcEndpointConfiguration register
endpoint 0 OUT
DcEndpointConfiguration register
endpoint 0 IN
DcEndpointConfiguration register
endpoint 1 to 14
DcEndpointConfiguration register
endpoint 0 OUT
DcEndpointConfiguration register
endpoint 0 IN
DcEndpointConfiguration register
endpoint 1 to 14
DcAddress register
DcMode register
DcInterruptEnable register
DcDMAConfiguration register
DcDMACounter register
resets all registers
Rev. 03 — 23 December 2004
Full-speed USB single-chip host and device controller
Code (Hex)
20
21
22 to 2F
30
31
32 to 3F
B6/B7
B8/B9
BA/BB
C2/C3
F0/F1
F2/F3
F6
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Transaction
write 1 word
write 1 word
write 1 word
read 1 word
read 1 word
read 1 word
write/read 1 word
write/read 1 word
write/read 1 word
write/read 2 words
write/read 1 word
write/read 1 word
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Table
ISP1161A
75.
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