ISP1161ABD-S ST-Ericsson Inc, ISP1161ABD-S Datasheet - Page 69

• Manufacturer Part Number: ISP1161ABD-S
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD-S

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
Table 42:
9397 750 13962
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcµPInterrupt register: bit allocation
reserved
R/W
R/W
15
0
7
0
10.4.4 HcµPInterrupt register (R/W: 24H/A4H)
ClkReady
All the bits in this register will be active on power-on reset. However, none of the
active bits will cause an interrupt on the interrupt pin (INT1) unless they are set by the
respective bits in the HcµPInterruptEnable register, and together with bit 0 of the
HcHardwareConfiguration register.
After this register (24H read) is read, the bits that are active will not be reset, until
logic 1 is written to the bits in this register (A4H - write) to clear it. To clear all the
enabled bits in this register, the HCD must write FFH to this register.
Code (Hex): 24 — read
Code (Hex): A4 — write
Table 43:
Bit
15 to 7
6
5
4
3
2
R/W
R/W
14
0
6
0
HcµPInterrupt register: bit description
Suspended
Symbol
-
ClkReady
HC
Suspended
OPR_Reg
-
AllEOT
Interrupt
R/W
R/W
HC
13
0
5
0
Rev. 03 — 23 December 2004
OPR_Reg
Description
reserved
0 — no event
1 — clock is ready. After a wake-up is sent, there is a wait for clock
ready. (Maximum is 1 ms, and typical is 160 µs)
0 — no event
1 — the HC has been suspended and no USB activity is sent from
the microprocessor for each ms. When the microprocessor wants
to suspend the HC, the microprocessor must write to the
HcControl register. And when all downstream devices are
suspended, then the HC stops sending SOF; the HC is suspended
by having the HcControl register written into.
0 — no event
1 — there are interrupts from HC side. Need to read HcControl
and HcInterrupt registers to detect type of interrupt on the HC (if
the HC requires the Operational register to be updated)
reserved
0 — no event
1 — implies that data transfer has been completed via PIO transfer
or DMA transfer. Occurrence of internal or external EOT will set
this bit.
Full-speed USB single-chip host and device controller
R/W
R/W
12
0
4
0
reserved
reserved
R/W
R/W
11
0
3
0
Interrupt
AllEOT
R/W
R/W
10
0
2
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
ATLInt
ISP1161A
R/W
R/W
9
0
1
0
SOFITLInt
R/W
R/W
68 of 134
8
0
0
0