DSPIC30F5015-30I/PT Microchip Technology Inc., DSPIC30F5015-30I/PT Datasheet - Page 130

• Manufacturer Part Number: DSPIC30F5015-30I/PT
• Description: DSP, 16-Bit, 66 KB Flash, 2KB RAM, 52 I/O, TQFP-64
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F5015-30I/PT

• A/d Inputs: 16-Channels, 10-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 52
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 52
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 66K Bytes
• Ram Size: 2K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC30F5015/5016
19.5.6
Transmit interrupts can be divided into 2 major groups,
each including various conditions that generate
interrupts:
• Transmit Interrupt
At least one of the three transmit buffers is empty (not
scheduled) and can be loaded to schedule a message
for transmission. Reading the TXnIF flags will indicate
which transmit buffer is available and caused the
interrupt.
• Transmit Error Interrupts
A transmission error interrupt will be indicated by the
ERRIF flag. This flag shows that an error condition
occurred. The source of the error can be determined by
checking the error flags in the CAN Interrupt Status
register, CiINTF. The flags in this register are related to
receive and transmit errors.
• Transmitter Warning Interrupt
• The TXWAR bit indicates that the Transmit Error
• Transmitter Error Passive
• The TXEP bit (CiINTF<12>) indicates that the
• Bus Off
• The TXBO bit (CiINTF<13>) indicates that the
FIGURE 19-2:
DS70149C-page 128
Input Signal
T
Counter has reached the CPU warning limit of 96
Transmit Error Counter has exceeded the error
passive limit of 127 and the module has gone to
Error Passive state
Transmit Error Counter has exceeded 255 and
the module has gone to Bus Off state
Q
TRANSMIT INTERRUPTS
Sync
CAN BIT TIMING
Segment
Prop
Segment 1
Phase
Sample Point
19.6
All nodes on any particular CAN bus must have the
same nominal bit rate. In order to set the baud rate, the
following parameters have to be initialized:
• Synchronization Jump Width
• Baud rate prescaler
• Phase segments
• Length determination of Phase2 Seg
• Sample Point
• Propagation segment bits
19.6.1
All controllers on the CAN bus must have the same
baud rate and bit length. However, different controllers
are not required to have the same master oscillator
clock. At different clock frequencies of the individual
controllers, the baud rate has to be adjusted by
adjusting the number of time quanta in each segment.
The Nominal Bit Time can be thought of as being
divided into separate non-overlapping time segments.
These segments are shown in Figure 19-2.
• Synchronization segment (Sync Seg)
• Propagation time segment (Prop Seg)
• Phase segment 1 (Phase1 Seg)
• Phase segment 2 (Phase2 Seg)
The time segments and also the nominal bit time are
made up of integer units of time called time quanta or
T
of 8 T
the minimum nominal bit time is 1 sec, corresponding
to a maximum bit rate of 1 MHz.
Q
. By definition, the Nominal Bit Time has a minimum
Q
and a maximum of 25 T
Baud Rate Setting
BIT TIMING
Segment 2
Phase
© 2007 Microchip Technology Inc.
Q
. Also, by definition,
Sync