DSPIC30F5015-30I/PT Microchip Technology Inc., DSPIC30F5015-30I/PT Datasheet - Page 17

• Manufacturer Part Number: DSPIC30F5015-30I/PT
• Description: DSP, 16-Bit, 66 KB Flash, 2KB RAM, 52 I/O, TQFP-64
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F5015-30I/PT

• A/d Inputs: 16-Channels, 10-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 52
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 52
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 66K Bytes
• Ram Size: 2K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

2.0
This
dsPIC30F5015/5016 CPU and peripheral function. For
a complete description of this functionality, please refer
to
(DS70046).
2.1
The core has a 24-bit instruction word. The Program
Counter (PC) is 23 bits wide with the Least Significant
bit (LSb) always clear (see Section 3.1 “Program
Address Space”), and the Most Significant bit (MSb)
is ignored during normal program execution, except for
certain specialized instructions. Thus, the PC can
address up to 4M instruction words of user program
space. An instruction prefetch mechanism is used to
help maintain throughput. Program loop constructs,
free from loop count management overhead, are
supported using the DO and REPEAT instructions, both
of which are interruptible at any point.
The working register array consists of 16x16-bit
registers, each of which can act as data, address or off-
set registers. One working register (W15) operates as
a software Stack Pointer for interrupts and calls.
The data space is 64 Kbytes (32K words) and is split
into two blocks, referred to as X and Y data memory.
Each block has its own independent Address Genera-
tion Unit (AGU). Most instructions operate solely
through the X memory AGU, which provides the
appearance of a single unified data space. The
Multiply-Accumulate (MAC) class of dual source DSP
instructions operate through both the X and Y AGUs,
splitting the data address space into two parts (see
Section 3.2 “Data Address Space”). The X and Y
data space boundary is device specific and cannot be
altered by the user. Each data word consists of 2 bytes,
and most instructions can address data either as words
or bytes.
© 2007 Microchip Technology Inc.
Note: This data sheet summarizes features of this
group of dsPIC30F devices and is not intended to be
a complete reference source. For more information
on the CPU, peripherals, register descriptions and
general device functionality, refer to the “dsPIC30F
Family Reference Manual” (DS70046). For more
information on the device instruction set and pro-
gramming, refer to the “dsPIC30F/33F Program-
mer’s Reference Manual” (DS70157).
the “dsPIC30F
document
CPU ARCHITECTURE
OVERVIEW
Core Overview
provides
Family
a
Reference
summary
Manual”
of
the
There are two methods of accessing data stored in
program memory:
• The upper 32 Kbytes of data space memory can be
• Linear indirect access of 32K word pages within
Overhead-free circular buffers (Modulo Addressing)
are supported in both X and Y address spaces. This is
primarily intended to remove the loop overhead for
DSP algorithms.
The X AGU also supports Bit-Reversed Addressing on
destination effective addresses, to greatly simplify input
or output data reordering for radix-2 FFT algorithms.
Refer to Section 4.0 “Address Generator Units” for
details on Modulo and Bit-Reversed Addressing.
The core supports Inherent (no operand), Relative, Lit-
eral, Memory Direct, Register Direct, Register Indirect,
Register Offset and Literal Offset Addressing modes.
Instructions are associated with predefined addressing
modes, depending upon their functional requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working reg-
ister (data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, 3-operand instructions are supported, allowing
C = A + B operations to be executed in a single cycle.
A DSP engine has been included to significantly
enhance the core arithmetic capability and throughput.
It features a high-speed 17-bit by 17-bit multiplier, a
40-bit ALU, two 40-bit saturating accumulators and a
40-bit bidirectional barrel shifter. Data in the accumula-
tor or any working register can be shifted up to 16 bits
right or 16 bits left in a single cycle. The DSP instruc-
tions operate seamlessly with all other instructions and
have been designed for optimal real-time performance.
The MAC class of instructions can concurrently fetch
two data operands from memory, while multiplying two
W registers. To enable this concurrent fetching of data
operands, the data space has been split for these
instructions and linear for all others. This has been
achieved in a transparent and flexible manner, by ded-
icating certain working registers to each address space
for the MAC class of instructions.
mapped into the lower half (user space) of program
space at any 16K program word boundary, defined
by the 8-bit Program Space Visibility Page
(PSVPAG) register. This lets any instruction access
program space as if it were data space, with a limi-
tation that the access requires an additional cycle.
Moreover, only the lower 16 bits of each instruction
word can be accessed using this method.
program space is also possible using any working
register, via table read and write instructions.
Table read and write instructions can be used to
access all 24 bits of an instruction word.
dsPIC30F5015/5016
DS70149C-page 15