DSPIC30F5015-30I/PT Microchip Technology Inc., DSPIC30F5015-30I/PT Datasheet - Page 159
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DSPIC30F5015-30I/PT
Manufacturer Part Number
DSPIC30F5015-30I/PT
Description
DSP, 16-Bit, 66 KB Flash, 2KB RAM, 52 I/O, TQFP-64
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F5015-30IPT.pdf
(230 pages)
Specifications of DSPIC30F5015-30I/PT
A/d Inputs
16-Channels, 10-Bit
Cpu Speed
30 MIPS
Eeprom Memory
1K Bytes
Input Output
52
Interface
CAN, I2C, SPI, UART/USART
Ios
52
Memory Type
Flash
Number Of Bits
16
Package Type
64-pin TQFP
Programmable Memory
66K Bytes
Ram Size
2K Bytes
Timers
5-16-bit, 2-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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21.9
The module has 3 internal power modes. When the
ADON bit is ‘1’, the module is in Active mode; it is fully
powered and functional. When ADON is ‘0’, the module
is in Off mode. The digital and analog portions of the
circuit are disabled for maximum current savings. In
order to return to the Active mode from Off mode, the
user must wait for the ADC circuitry to stabilize.
21.10 ADC Operation During CPU Sleep
21.10.1
When the device enters Sleep mode, all clock sources
to the module are shutdown and stay at logic ‘0’.
If Sleep occurs in the middle of a conversion, the con-
version is aborted. The converter will not continue with
a partially completed conversion on exit from Sleep
mode.
Register contents are not affected by the device
entering or leaving Sleep mode.
The ADC module can operate during Sleep mode if the
ADC clock source is set to RC (ADRC = 1). When the
RC clock source is selected, the ADC module waits
one instruction cycle before starting the conversion.
This allows the SLEEP instruction to be executed,
which eliminates all digital switching noise from the
conversion. When the conversion is complete, the
DONE bit will be set and the result loaded into the
ADCBUF register.
FIGURE 21-4:
© 2007 Microchip Technology Inc.
RAM Contents:
Read to Bus:
Signed Fractional (1.15)
Module Power-Down Modes
and Idle Modes
ADC OPERATION DURING CPU
SLEEP MODE
Fractional (1.15)
Signed Integer
Integer
ADC OUTPUT DATA FORMATS
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
0
0
0
0
0
0
If the A/D interrupt is enabled, the device will wake-up
from Sleep. If the A/D interrupt is not enabled, the A/D
module will then be turned off, although the ADON bit
will remain set.
21.10.2
The ADSIDL bit selects if the module will stop on Idle or
continue on Idle. If ADSIDL = 0, the module will continue
operation on assertion of Idle mode. If ADSIDL = 1, the
module will stop on Idle.
21.11 Effects of a Reset
A device Reset forces all registers to their Reset state.
This forces the ADC module to be turned off, and any
conversion and acquisition sequence is aborted. The
values that are in the ADCBUF registers are not modi-
fied. The ADC result register will contain unknown data
after a Power-on Reset.
21.12 Output Formats
The ADC result is 10 bits wide. The data buffer RAM is
also 10 bits wide. The 10-bit data can be read in one of
four different formats. The FORM<1:0> bits select the
format. Each of the output formats translates to a 16-bit
result on the data bus.
Write data will always be in right justified (integer)
format.
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
d09 d08 d07 d06 d05 d04 d03 d02 d01 d00
dsPIC30F5015/5016
ADC OPERATION DURING CPU
IDLE MODE
0
0
0
0
0
0
DS70149C-page 157
0
0
0
0
0
0
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