DSPIC30F5015-30I/PT Microchip Technology Inc., DSPIC30F5015-30I/PT Datasheet - Page 142
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DSPIC30F5015-30I/PT
Manufacturer Part Number
DSPIC30F5015-30I/PT
Description
DSP, 16-Bit, 66 KB Flash, 2KB RAM, 52 I/O, TQFP-64
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F5015-30IPT.pdf
(230 pages)
Specifications of DSPIC30F5015-30I/PT
A/d Inputs
16-Channels, 10-Bit
Cpu Speed
30 MIPS
Eeprom Memory
1K Bytes
Input Output
52
Interface
CAN, I2C, SPI, UART/USART
Ios
52
Memory Type
Flash
Number Of Bits
16
Package Type
64-pin TQFP
Programmable Memory
66K Bytes
Ram Size
2K Bytes
Timers
5-16-bit, 2-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Part Number:
DSPIC30F5015-30I/PT
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Microchip Technology
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dsPIC30F5015/5016
20.3.1
A power-on event will generate an internal POR pulse
when a V
at the POR circuit threshold voltage (V
nominally 1.85V. The device supply voltage character-
istics must meet specified starting voltage and rise rate
requirements. The POR pulse will reset a POR timer
and place the device in the Reset state. The POR also
selects the device clock source identified by the
oscillator configuration fuses.
FIGURE 20-3:
FIGURE 20-4:
DS70149C-page 140
PWRT Time-out
PWRT Time-out
OST Time-out
Internal Reset
OST Time-out
Internal Reset
DD
Internal POR
Internal POR
POR: POWER-ON RESET
rise is detected. The Reset pulse will occur
MCLR
MCLR
V
V
DD
DD
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V
POR
), which is
T
T
OST
OST
T
PWRT
T
PWRT
The POR circuit inserts a small delay, T
nominally 10
circuits are stable. Furthermore, a user selected power-
up time-out (T
is based on Configuration bits and can be 0 ms (no
delay), 4 ms, 16 ms or 64 ms. The total delay is at
device power-up T
have expired, SYSRST will be negated on the next
leading edge of the Q1 clock, and the PC will jump to
the Reset vector.
The timing for the SYSRST signal is shown in
Figure 20-3 through Figure 20-5.
PWRT
s and ensures that the device bias
POR
) is applied. The T
© 2007 Microchip Technology Inc.
+ T
DD
PWRT
)
. When these delays
DD
): CASE 1
PWRT
POR
parameter
, which is
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