DSPIC30F5015-30I/PT Microchip Technology Inc., DSPIC30F5015-30I/PT Datasheet - Page 20

• Manufacturer Part Number: DSPIC30F5015-30I/PT
• Description: DSP, 16-Bit, 66 KB Flash, 2KB RAM, 52 I/O, TQFP-64
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F5015-30I/PT

• A/d Inputs: 16-Channels, 10-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 52
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 52
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 66K Bytes
• Ram Size: 2K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC30F5015/5016
2.3
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and
16/16-bit
operations, in the form of single instruction iterative
divides. The following instructions and data sizes are
supported:
1.
2.
3.
4.
5.
TABLE 2-1:
2.4
The DSP engine consists of a high-speed 17-bit x 17-bit
multiplier, a barrel shifter, and a 40-bit adder/subtracter
(with two target accumulators, round and saturation
logic).
The dsPIC30F devices have a single instruction flow
which can execute either DSP or MCU instructions.
Many of the hardware resources are shared between
the DSP and MCU instructions. For example, the
instruction set has both DSP and MCU multiply
instructions which use the same hardware multiplier.
The DSP engine also has the capability to perform inher-
ent accumulator-to-accumulator
require no additional data. These instructions are ADD,
SUB and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Configuration register
(CORCON), as listed below:
1.
2.
3.
4.
5.
6.
7.
DS70149C-page 18
DIVF
DIV.sd
DIV.ud
DIV.sw
DIV.uw
Note:
DIVF – 16/16 signed fractional divide
DIV.sd – 32/16 signed divide
DIV.ud – 32/16 unsigned divide
DIV.sw – 16/16 signed divide
DIV.uw – 16/16 unsigned divide
Fractional or Integer DSP Multiply (IF).
Signed or Unsigned DSP Multiply (US).
Conventional or Convergent Rounding (RND).
Automatic Saturation On/Off for ACCA (SATA).
Automatic Saturation On/Off for ACCB (SATB).
Automatic Saturation On/Off for Writes to Data
Memory (SATDW).
Accumulator
(ACCSAT).
Divide Support
DSP Engine
signed
For CORCON layout, see Table 3-3.
Instruction
DIVIDE INSTRUCTIONS
Saturation
and
unsigned
mode
operations,
integer
Signed fractional divide: Wm/Wn
Signed divide: (Wm+1:Wm)/Wn
Unsigned divide: (Wm+1:Wm)/Wn
Signed divide: Wm/Wn
Unsigned divide: Wm/Wn
Selection
divide
which
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g. a series
of discrete divide instructions) will not function correctly
because the instruction flow depends on RCOUNT. The
divide instruction does not automatically set up the
RCOUNT value, and it must, therefore, be explicitly and
correctly specified in the REPEAT instruction, as shown
in Table 2-1 (REPEAT will execute the target instruction
{operand value+1} times). The REPEAT loop count must
be set up for 18 iterations of the DIV/DIVF instruction.
Thus, a complete divide operation requires 19 cycles.
A block diagram of the DSP engine is shown in
Figure 2-2.
TABLE 2-2:
CLR
ED
EDAC
MAC
MOVSAC
MPY
MPY.N
MSC
Note:
Instruction
W0; Rem
W0; Rem
Function
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
W0; Rem
W0; Rem
W0; Rem
W1
DSP INSTRUCTION
SUMMARY
W1
© 2007 Microchip Technology Inc.
W1
Algebraic Operation
W1
W1
A = 0
A = (x – y)
A = A + (x – y)
A = A + (x * y)
No change in A
A = x * y
A = – x * y
A = A – x * y
2
2