DSPIC30F5015-30I/PT Microchip Technology Inc., DSPIC30F5015-30I/PT Datasheet - Page 44

• Manufacturer Part Number: DSPIC30F5015-30I/PT
• Description: DSP, 16-Bit, 66 KB Flash, 2KB RAM, 52 I/O, TQFP-64
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F5015-30I/PT

• A/d Inputs: 16-Channels, 10-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 52
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 52
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 66K Bytes
• Ram Size: 2K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

dsPIC30F5015/5016
5.1
The user assignable Interrupt Priority (IP<2:0>) bits for
each individual interrupt source are located in the Least
Significant 3 bits of each nibble within the IPCx regis-
ter(s). Bit 3 of each nibble is not used and is read as a
‘0’. These bits define the priority level assigned to a
particular interrupt by the user.
Since more than one interrupt request source may be
assigned to a specific user specified priority level, a
means is provided to assign priority within a given level.
This method is called “Natural Order Priority”.
Natural Order Priority is determined by the position of
an interrupt in the vector table, and only affects
interrupt operation when multiple interrupts with the
same user-assigned priority become pending at the
same time.
Table 5-1 lists the interrupt numbers and interrupt
sources for the dsPIC DSC devices and their
associated vector numbers.
The ability for the user to assign every interrupt to one
of seven priority levels means that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority.
DS70149C-page 42
Note:
Note 1: The Natural Order Priority scheme has 0
2: The Natural Order Priority number is the
Interrupt Priority
The user-selectable priority levels start at
0, as the lowest priority and level 7, as the
highest priority.
as the highest priority and 53 as the
lowest priority.
same as the INT number.
TABLE 5-1:
Highest Natural Order Priority
Lowest Natural Order Priority
Number
45-53
INT
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
11
0
1
2
3
4
5
6
7
8
9
Number
Vector
53-61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
8
9
INTERRUPT VECTOR TABLE
INT0 – External Interrupt 0
IC1 – Input Capture 1
OC1 – Output Compare 1
T1 – Timer1
IC2 – Input Capture 2
OC2 – Output Compare 2
T2 – Timer2
T3 – Timer3
SPI1
U1RX – UART1 Receiver
U1TX – UART1 Transmitter
ADC – ADC Convert Done
NVM – NVM Write Complete
SI2C – I
MI2C – I
Input Change Interrupt
INT1 – External Interrupt 1
Reserved
Reserved
OC3 – Output Compare 3
OC4 – Output Compare 4
T4 – Timer4
T5 – Timer5
INT2 – External Interrupt 2
Reserved
Reserved
SPI2
C1 – Combined IRQ for CAN1
IC3 – Input Capture 3
IC4 – Input Capture 4
Reserved
Reserved
OC5 – Output Compare 5
OC6 – Output Compare 6
OC7 – Output Compare 7
OC8 – Output Compare 8
INT3 – External Interrupt 3
INT4 – External Interrupt 4
Reserved
PWM – PWM Period Match
QEI – QEI Interrupt
Reserved
Reserved
FLTA – PWM Fault A
FLTB – PWM Fault B
Reserved
© 2007 Microchip Technology Inc.
2
Interrupt Source
2
C™ Slave Interrupt
C Master Interrupt