DSPIC30F5015-30I/PT Microchip Technology Inc., DSPIC30F5015-30I/PT Datasheet - Page 223

• Manufacturer Part Number: DSPIC30F5015-30I/PT
• Description: DSP, 16-Bit, 66 KB Flash, 2KB RAM, 52 I/O, TQFP-64
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F5015-30I/PT

• A/d Inputs: 16-Channels, 10-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 52
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 52
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 66K Bytes
• Ram Size: 2K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

I
I
I
I
M
Memory Organization ......................................................... 23
Microchip Internet Web Site ............................................. 225
Modulo Addressing ............................................................ 36
Motor Control PWM Module ............................................... 93
MPLAB ASM30 Assembler, Linker, Librarian .................. 170
MPLAB ICD 2 In-Circuit Debugger .................................. 171
MPLAB ICE 2000 High-Performance Universal
MPLAB ICE 4000 High-Performance Universal
MPLAB Integrated Development Environment Software . 169
MPLAB PM3 Device Programmer ................................... 171
MPLINK Object Linker/MPLIB Object Librarian ............... 170
N
NVM
O
Operating Current (I
Oscillator
Oscillator Configurations .................................................. 136
Oscillator Selection .......................................................... 133
© 2007 Microchip Technology Inc.
2
2
2
2
C Master Mode
C Module ....................................................................... 107
C 10-bit Slave Mode Operation ..................................... 109
C 7-bit Slave Mode Operation ....................................... 109
Baud Rate Generator ............................................... 111
Clock Arbitration ....................................................... 112
Multi-Master Communication, Bus Collision
Reception ................................................................. 111
Transmission ............................................................ 111
Addresses ................................................................ 109
General Call Address Support ................................. 111
Interrupts .................................................................. 111
IPMI Support ............................................................ 111
Master Operation ..................................................... 111
Master Support ........................................................ 111
Operating Function Description ............................... 107
Operation During CPU Sleep and Idle Modes ......... 112
Pin Configuration ..................................................... 107
Programmer’s Model ................................................ 107
Register Map ............................................................ 113
Registers .................................................................. 107
Slope Control ........................................................... 111
Software Controlled Clock Stretching (STREN = 1) . 110
Various Modes ......................................................... 107
Reception ................................................................. 110
Transmission ............................................................ 110
Reception ................................................................. 109
Transmission ............................................................ 109
Applicability ................................................................ 38
Operation Example .................................................... 37
Start and End Address ............................................... 37
W Address Register Selection ................................... 37
In-Circuit Emulator ................................................... 171
In-Circuit Emulator ................................................... 171
Register Map .............................................................. 53
Operating Modes (Table) ......................................... 134
System Overview ..................................................... 133
Fail-Safe Clock Monitor ............................................ 138
Fast RC (FRC) ......................................................... 137
Initial Clock Source Selection .................................. 136
Low-Power RC (LPRC) ............................................ 138
LP Oscillator Control ................................................ 137
Phase Locked Loop (PLL) ....................................... 137
Start-up Timer (OST) ............................................... 137
and Bus Arbitration .......................................... 112
DD
) .................................................... 176
Output Compare Module ................................................... 83
P
Packaging
Peripheral Module Disable (PMD) Registers ................... 146
PICSTART Plus Development Programmer .................... 172
Pinout Descriptions
POR. See Power-on Reset.
Port Write/Read Example .................................................. 60
Position Measurement Mode ............................................. 88
Power-Down Current (I
Power-on Reset (POR) .................................................... 133
Power-Saving Modes ....................................................... 144
Power-Saving Modes (Sleep and Idle) ............................ 133
Program Address Space .................................................... 23
Program Counter ............................................................... 16
Program Data Table Access (MSB) ................................... 26
Program Space Visibility
Programmable ................................................................. 133
Programmable Digital Noise Filters ................................... 89
Programmer’s Model ......................................................... 16
Protection Against Accidental Writes to OSCCON .......... 139
PWM
dsPIC30F5015/5016
Interrupts ................................................................... 85
Operation During CPU Idle Mode .............................. 85
Operation During CPU Sleep Mode .......................... 85
Register Map ............................................................. 86
Timer2, Timer3 Selection Mode ................................ 84
Information ............................................................... 213
Marking .................................................................... 213
dsPIC30F5015 ............................................................. 9
dsPIC30F5016 ........................................................... 12
Oscillator Start-up Timer (OST) ............................... 133
Power-up Timer (PWRT) ......................................... 133
Idle ........................................................................... 145
Sleep ....................................................................... 144
Construction .............................................................. 24
Data Access from Program Memory Using
Data Access from Program Memory Using
Data Access from, Address Generation .................... 24
Memory Map .............................................................. 23
Table Instructions
Window into Program Space Operation .................... 27
Center-Aligned ........................................................... 97
Complementary Operation ........................................ 98
Dead-Time Generators .............................................. 98
Duty Cycle Comparison Units .................................... 97
Edge-Aligned ............................................................. 96
Fault Pins ................................................................. 100
Independent Output ................................................... 99
Operation During CPU Idle Mode ............................ 101
Program Space Visibility .................................... 26
Table Instructions .............................................. 25
TBLRDH ............................................................ 25
TBLRDL ............................................................. 25
TBLWTH ............................................................ 25
TBLWTL ............................................................ 25
Assignment ........................................................ 98
Ranges .............................................................. 98
Selection Bits ..................................................... 98
Immediate Updates ........................................... 97
Register Buffers ................................................. 97
Enable Bits ...................................................... 100
Fault States ..................................................... 100
Input Modes ..................................................... 100
Priority ............................................................. 100
PD
) ............................................... 178
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