DSPIC30F5015-30I/PT Microchip Technology Inc., DSPIC30F5015-30I/PT Datasheet - Page 98

• Manufacturer Part Number: DSPIC30F5015-30I/PT
• Description: DSP, 16-Bit, 66 KB Flash, 2KB RAM, 52 I/O, TQFP-64
• Manufacturer: Microchip Technology Inc.
• Type: DSPr

Specifications of DSPIC30F5015-30I/PT

• A/d Inputs: 16-Channels, 10-Bit
• Cpu Speed: 30 MIPS
• Eeprom Memory: 1K Bytes
• Input Output: 52
• Interface: CAN, I2C, SPI, UART/USART
• Ios: 52
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin TQFP
• Programmable Memory: 66K Bytes
• Ram Size: 2K Bytes
• Timers: 5-16-bit, 2-32-bit
• Voltage, Range: 2.5-5.5
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

buffered register. The PTPER buffer contents are loaded
dsPIC30F5015/5016
15.1.4
In the Double Update mode (PTMOD<1:0> = 11), an
interrupt event is generated each time the PTMR regis-
ter is equal to zero, as well as each time a period match
occurs. The postscaler selection bits have no effect in
this mode of the timer.
The Double Update mode provides two additional func-
tions to the user. First, the control loop bandwidth is
doubled because the PWM duty cycles can be
updated, twice per period. Second, asymmetrical
center-aligned PWM waveforms can be generated,
which are useful for minimizing output waveform
distortion in certain motor control applications.
15.1.5
The input clock to PTMR (F
options of 1:1, 1:4, 1:16, or 1:64, selected by control
bits PTCKPS<1:0> in the PTCON SFR. The prescaler
counter is cleared when any of the following occurs:
• a write to the PTMR register
• a write to the PTCON register
• any device Reset
PTMR is not cleared when PTCON is written.
15.1.6
The match output of PTMR can optionally be post-
scaled through a 4-bit postscaler (which gives a 1:1 to
1:16 scaling).
The postscaler counter is cleared when any of the
following occurs:
• a write to the PTMR register
• a write to the PTCON register
• any device Reset
The PTMR register is not cleared when PTCON is written.
15.2
PTPER is a 15-bit register and is used to set the counting
period for the PWM time base. PTPER is a double-
into the PTPER register at the following instants:
• Free-Running and Single-Shot modes: When the
• Up/Down Counting modes: When the PTMR
The value held in the PTPER buffer is automatically
loaded into the PTPER register when the PWM time
base is disabled (PTEN = 0).
The
Equation 15-1:
DS70149C-page 96
Note:
PTMR register is reset to zero after a match with
the PTPER register.
register is zero.
PWM
PWM Period
DOUBLE UPDATE MODE
Programming a value of 0x0001 in the
Period register could generate a continu-
ous interrupt pulse and hence, must be
avoided.
PWM TIME BASE PRESCALER
PWM TIME BASE POSTSCALER
period
can
be
OSC
determined
/4), has prescaler
using
EQUATION 15-1:
If the PWM time base is configured for one of the Up/
Down Count modes, the PWM period is given by
Equation 15-2.
EQUATION 15-2:
The maximum resolution (in bits) for a given device
oscillator and PWM frequency can be determined using
Equation 15-3:
EQUATION 15-3:
15.3
Edge-aligned PWM signals are produced by the module
when the PWM time base is in the Free-Running or
Single-Shot mode. For edge-aligned PWM outputs, the
output has a period specified by the value in PTPER
and a duty cycle specified by the appropriate Duty Cycle
register (see Figure 15-2). The PWM output is driven
active at the beginning of the period (PTMR = 0) and is
driven inactive when the value in the Duty Cycle register
matches PTMR.
If the value in a particular Duty Cycle register is zero,
then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the out-
put on the PWM pin will be active for the entire PWM
period if the value in the Duty Cycle register is greater
than the value held in the PTPER register.
FIGURE 15-2:
PTPER
0
Resolution =
Edge-Aligned PWM
T
T
PWM
Duty Cycle
PWM
PTMR
Value
=
=
Period
(PTMR Prescale Value)
(PTMR Prescale Value)
2 • T
T
PWM PERIOD
PWM PERIOD (UP/DOWN
MODE)
PWM RESOLUTION
EDGE-ALIGNED PWM
CY
© 2007 Microchip Technology Inc.
log (2
CY
•
New Duty Cycle Latched
(PTPER + 1)
• (PTPER + 1)
log (2)
•
T
PWM
/T
CY
)