DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 175

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 2 to 0: Receive Spare Code Length Definition Bits (RSC[2:0])
Bit #
Name
Default
Bit 7 (T1 Mode): Receive HDLC-256 Mode Select (RHMS)
Bit 7 (E1 Mode): Receive HDLC-256 Mode Select (RHMS)
Bit 6: Receive HDLC-256 Enable (RHEN)
Bit 2: Receive BERT Port Direction Control (RBPDIR)
Bit 1: Receive BERT Port Framed/Unframed Select (RBPFUS) (T1 Mode Only)
Bit 0: Receive BERT Port Enable (RBPEN)
RSC2
0
0
0
0
1
1
1
1
0 = Receive HDLC-256 assigned to time slots
1 = Receive HDLC-256 assigned to FDL bits
0 = Receive HDLC-256 assigned to time slots
1 = Receive HDLC-256 assigned to the Sa bits
0 = Receive HDLC-256 is not active.
1 = Receive HDLC-256 is active.
0 = Normal (line) operation. Rx BERT port receives data from the receive framer.
1 = System (backplane) operation. Rx BERT port receives data from the transmit path. The transmit path
enters the receive BERT on the line side of the elastic store (if enabled).
0 = The DS26518’s receive BERT will not clock data from the F-bit position (framed).
1 = The DS26518’s receive BERT will clock data from the F-bit position (unframed).
0 = Receive BERT port is not active.
1 = Receive BERT port is active.
RSC1
0
0
1
1
0
0
1
1
RHMS
RHMS
—
7
0
7
0
RSC0
0
1
0
1
0
1
0
1
T1RSCC (T1 Mode Only)
In-Band Receive Spare Control Register
089h + (200h x (n - 1)) : where n = 1 to 8
RXPC
Receive Expansion Port Control Register (HDLC-256)
08Ah + (200h x (n - 1)) : where n = 1 to 8
RHEN
RHEN
—
6
0
6
0
LENGTH SELECTED
—
—
—
5
0
5
0
8 : 16 bits
1 bits
2 bits
3 bits
4 bits
5 bits
6 bits
7 bits
175 of 312
—
—
—
0
0
4
4
—
—
—
3
0
3
0
RBPDIR
RBPDIR
RSC2
2
0
2
0
RBPFUS
RSC1
—
1
0
1
0
RBPEN
RBPEN
RSC0
0
0
0
0