DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 209

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
The Transmit Channel Idle Code Enable Registers (TCICE1–4) are used to determine which of the 24 T1 channels
(or 32 E1 channels) from the backplane should be overwritten with the code placed in the Transmit Idle Code
Definition Register (TIDR1–32).
Bits 7 to 0: Transmit Channels 1 to 32 Code Insertion Control Bits (CH[1:32])
Register Name:
Register Description:
Register Address:
Bit #
Name
The Transmit Jammed Bit Eight Stuffing Registers (TJBE1–4) select which of the 24 T1 channels (or 32 E1
Channels) to insert jammed bit eight stuffing. These registers are enabled by TCR4.TJBEN.
Bits 7 to 0: Transmit Channels 1 to 32 Jammed Bit Eight Stuffing Control Bits (CH[1:32])
Register Name:
Register Description:
Register Address:
The Transmit DDS Zero Code Registers (TDDS1–3) select which of the 24 T1 channels to insert DDS zero code
stuffing. These registers are enabled by T1.TCR2.TDDSEN.
Bits 7 to 0: Transmit Channels 1 to 24 DDS Zero Code Control Bits (CH[1:32])
(MSB)
CH16
CH24
CH8
0 = Do not insert data from the Idle Code Array into the transmit data stream.
1 = Insert data from the Idle Code Array into the transmit data stream.
0 = Do not affect data in this channel.
1 = Replace the channel with TJBES if the channel is all zeros.
0 = Do not affect data in this channel.
1 = Replace the channel with DDS Zero Code stuffing if the channel is all zeros.
(MSB)
(MSB)
CH16
CH24
CH32
CH16
CH24
CH32
CH15
CH23
CH8
CH8
CH7
7
7
CH15
CH23
CH31
CH15
CH23
CH31
CH14
CH22
CH7
CH7
CH6
TCICE1, TCICE2, TCICE3, TCICE4
Transmit Channel Idle Code Enable Registers 1 to 4
150h, 151h, 152h, 153h + (200h x (n - 1)) : where n = 1 to 8
TJBE1, TJBE2, TJBE3, TJBE4
Transmit Jammed Bit Eight Stuffing Registers 1 to 4
104h, 105h, 106h, 107h + (200h x (n - 1)) : where n = 1 to 8
TDDS1, TDDS2, TDDS3
Transmit DDS Zero Code Registers 1 to 3
108h, 109h, 10Ah + (200h x (n - 1)) : where n = 1 to 8
6
6
CH14
CH22
CH30
CH14
CH22
CH30
CH13
CH21
CH6
CH6
CH5
5
5
CH13
CH21
CH29
CH13
CH21
CH29
CH12
CH20
CH5
CH5
CH4
4
4
209 of 312
CH12
CH20
CH28
CH12
CH20
CH28
CH11
CH19
CH3
CH4
CH4
3
3
CH11
CH19
CH27
CH11
CH19
CH27
CH10
CH18
CH3
CH3
CH2
2
2
(LSB)
CH17
CH10
CH18
CH26
CH10
CH18
CH26
CH1
CH9
CH2
CH2
1
1
TDDS1
TDDS2
TDDS3
(LSB)
CH17
CH25
(LSB)
CH17
CH25
CH1
CH9
CH1
CH9
0
0
TCICE1
TCICE2
TCICE3
TCICE4 (E1
Mode Only)
TJBE1
TJBE2
TJBE3
TJBE4