DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 6

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS26518 8-Port T1/E1/J1 Transceiver
Figure 11-16. T1 Transmit-Side TCHCLKn Gapped Mode During F-Bit ................................................................. 281
Figure 11-17. E1 Receive-Side Timing.................................................................................................................... 282
Figure 11-18. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................ 282
Figure 11-19. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................ 283
Figure 11-20. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)............................................ 283
Figure 11-21. E1 Receive-Side Interleave Bus Operation—BYTE Mode ............................................................... 284
Figure 11-22. E1 Receive-Side Interleave Bus Operation—FRAME Mode ............................................................ 285
Figure 11-23. E1 Receive-Side RCHCLKn Gapped Mode During Channel 1 ........................................................ 285
Figure 11-24. E1 Transmit-Side Timing................................................................................................................... 286
Figure 11-25. E1 Transmit-Side Boundary Timing (Elastic Store Disabled) ........................................................... 286
Figure 11-26. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)........................................... 287
Figure 11-27. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)........................................... 287
Figure 11-28. E1 Transmit-Side Interleave Bus Operation—BYTE Mode .............................................................. 288
Figure 11-29. E1 Transmit-Side Interleave Bus Operation—FRAME Mode ........................................................... 289
Figure 11-30. E1 G.802 Timing ............................................................................................................................... 290
Figure 11-31. E1 Transmit-Side TCHCLKn Gapped Mode During Channel 1 ........................................................ 290
Figure 13-1. SPI Interface Timing Diagram ............................................................................................................. 294
Figure 13-2. Intel Bus Read Timing (BTS = 0) ........................................................................................................ 296
Figure 13-3. Intel Bus Write Timing (BTS = 0)......................................................................................................... 296
Figure 13-4. Motorola Bus Read Timing (BTS = 1) ................................................................................................. 297
Figure 13-5 Motorola Bus Write Timing (BTS = 1) .................................................................................................. 297
Figure 13-6. Receive Framer Timing—Backplane (T1 Mode)................................................................................. 299
Figure 13-7. Receive-Side Timing—Elastic Store Enabled (T1 Mode) ................................................................... 299
Figure 13-8. Transmit Formatter Timing—Backplane ............................................................................................. 301
Figure 13-9. Transmit Formatter Timing—Elastic Store Enabled............................................................................ 302
Figure 13-10. BPCLK1 Timing................................................................................................................................. 302
Figure 13-11. JTAG Interface Timing Diagram........................................................................................................ 303
Figure 14-1. JTAG Functional Block Diagram ......................................................................................................... 304
Figure 14-2. TAP Controller State Diagram............................................................................................................. 307
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