DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 72

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.9.16 T1 Programmable In-Band Loop Code Detection
The DS26518 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This
function is available only in T1 mode.
Table 9-34. Registers Related to T1 In-Band Loop Code Detection
Receive In-Band Code Control Register
(T1RIBCC)
Receive Up Code Definition Register 1
(T1RUPCD1)
Receive Up Code Definition Register 2
(T1RUPCD2)
Receive Down Code Definition Register 1
(T1RDNCD1)
Receive Down Code Definition Register 2
(T1RDNCD2)
Receive Spare Code Register 1 (T1RSCD1)
Receive Spare Code Register 2 (T1RSCD2)
Receive Real-Time Status Register 3 (RRTS3)
Receive Latched Status Register 3 (RLS3)
Receive Interrupt Mask Register 3 (RIM3)
Note: The addresses shown above are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200hex), where n = 2 to 8 for Framers 2 to 8.
The framer has three programmable pattern detectors. Typically, two of the detectors are used for “loop-up” and
“loop-down” code detection. The user will program the codes to be detected in the Receive Up Code Definition
Registers 1 and 2
(T1RDNCD1
There is a third detector (spare) and it is defined and controlled via the
registers. When detecting a 16-bit pattern both receive code definition registers are used together to form a 16-bit
register. For 8-bit patterns, both receive code definition registers will be filled with the same value. Detection of a
1-, 2-, 3-, 4-, 5-, 6-, and 7-bit pattern only requires the first receive code definition register to be filled. The framer
will detect repeating pattern codes in both framed and unframed circumstances with bit error rates as high as
10E–2. The detectors can handle both F-bit inserted and F-bit overwrite patterns. Writing the least significant byte
of receive code definition register resets the integration period for that detector. The code detector has a nominal
integration period of 48ms. Hence, after about 48ms of receiving a valid code, the proper status bit (LUP, LDN, and
LSP) will be set to a one. Note that real-time status bits, as well as latched set and clear bits are available for LUP,
LDN and LSP
software poll the framer every 50ms to 100ms until 5 seconds has elapsed to ensure that the code is continuously
present.
and T1RDNCD2) registers and the length of each pattern will be selected via the
(RRTS3
REGISTER
(T1RUPCD1
and RLS3). Normally codes are sent for a period of 5 seconds. It is recommend that the
and T1RUPCD2) and the Receive Down Code Definition Registers 1 and 2
72 of 312
ADDRESSES
FRAMER 1
0ACh
0ADh
0AEh
0AFh
09Ch
09Dh
0B2h
0A2h
082h
092h
Used for selecting length of receive in-
band loop code register.
Receive up code definition register 1.
Receive up code definition register 2.
Receive down code definition register 1.
Receive up code definition register 2.
Receive spare code register 1.
Receive spare code register 2.
Real-time loop code detect.
Latched loop code detect bits.
Mask for latched loop code detect bits.
T1RSCD1/T1RSCD2
FUNCTION
T1RIBCC
and
T1RSCC
register.