PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 131

• Manufacturer Part Number: PIC16F913-I/SP
• Description: 28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F913-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

11.1
The BRG supports both the Asynchronous and
Synchronous modes of the USART. It is a dedicated
8-bit baud rate generator. The SPBRG register controls
the period of a free running 8-bit timer. In
Asynchronous mode, bit BRGH (TXSTA<2>) also
controls the baud rate. In Synchronous mode, bit
BRGH is ignored. Table 11-1 shows the formula for
computation of the baud rate for different USART
modes which only apply in Master mode (internal
clock).
Given the desired baud rate and F
integer value for the SPBRG register can be calculated
using the formula in Table 11-1. From this, the error in
baud rate can be determined.
TABLE 11-1:
TABLE 11-2:
© 2005 Microchip Technology Inc.
98h
18h
99h
Legend: x = unknown,
Legend: X = value in SPBRG (0 to 255)
Address
SYNC
0
1
USART Baud Rate Generator
(BRG)
TXSTA
RCSTA
SPBRG Baud Rate Generator Register
Name
(Asynchronous) Baud Rate = F
(Synchronous) Baud Rate = F
BAUD RATE FORMULA
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
CSRC
SPEN
Bit 7
-
BRGH = 0 (Low Speed)
= unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
Bit 6
RX9
TX9
OSC
SREN CREN ADDEN
TXEN SYNC
Bit 5
, the nearest
OSC
OSC
Bit 4
Preliminary
/(64 (X + 1))
/(4 (X + 1))
PIC16F917/916/914/913
Bit 3
—
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the F
baud rate error in some cases.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures the
BRG does not wait for a timer overflow before
outputting the new baud rate.
11.1.1
The data on the RC7/RX/DT/SDI/SDA/SEG8 pin is
sampled three times by a majority detect circuit to
determine if a high or a low level is present at the RX
pin.
BRGH TRMT TX9D 0000 -010 0000 -010
FERR
Bit 2
OERR RX9D 0000 000x 0000 000x
SAMPLING
Bit 1
Baud Rate = F
OSC
BRGH = 1 (High Speed)
/(16 (X + 1)) equation can reduce the
Bit 0
N/A
OSC
0000 0000 0000 0000
POR, BOR
Value on:
/(16 (X + 1))
DS41250E-page 129
Value on
all other
Resets