PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 147

• Manufacturer Part Number: PIC16F913-I/SP
• Description: 28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F913-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

12.1.5
The A/D conversion is initiated by setting the
GO/DONE bit (ADCON0<1>). When the conversion is
complete, the A/D module:
• Clears the GO/DONE bit
• Sets the ADIF flag (PIR1<6>)
• Generates an interrupt (if enabled)
If the conversion must be aborted, the GO/DONE bit
can be cleared in software. The ADRESH:ADRESL
registers will not be updated with the partially complete
A/D
ADRESH:ADRESL registers will retain the value of the
previous conversion. After an aborted conversion, a
2 T
be initiated. Following the delay, an input acquisition is
automatically started on the selected channel.
FIGURE 12-2:
12.1.6
The A/D conversion can be supplied in two formats: left
or right shifted. The ADFM bit (ADCON0<7>) controls
the output format. Figure 12-3 shows the output
formats.
FIGURE 12-3:
© 2005 Microchip Technology Inc.
Note:
AD
(ADFM = 0)
(ADFM = 1)
delay is required before another acquisition can
conversion
STARTING A CONVERSION
The GO/DONE bit should not be set in the
same instruction that turns on the A/D.
CONVERSION OUTPUT
T
CY TO
Set GO/DONE bit
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
T
AD
MSB
bit 7
bit 7
Conversion Starts
A/D CONVERSION T
10-BIT A/D RESULT FORMAT
Unimplemented: Read as ‘0’
T
AD
sample.
1 T
AD
b9
2 T
AD
b8
Instead,
ADRESH
3 T
10-bit A/D Result
AD
b7
AD
4 T
CYCLES
Preliminary
the
AD
b6
5 T
MSB
PIC16F917/916/914/913
AD
b5
bit 0
bit 0
6 T
ADRESH and ADRESL registers are loaded,
GO/DONE bit is cleared,
ADIF bit is set,
Holding Capacitor is Connected to Analog Input
AD
b4
7 T
bit 7
bit 7
AD
b3
8 T
10-bit A/D Result
LSB
AD
b2
9
T
Unimplemented: Read as ‘0’
AD
b1
10 T
ADRESL
AD
b0
11
DS41250E-page 145
bit 0
LSB
bit 0