PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 81

• Manufacturer Part Number: PIC16F913-I/SP
• Description: 28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F913-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 4-7:
4.7
The Fail-Safe Clock Monitor (FSCM) is designed to
allow the device to continue to operate in the event of
an oscillator failure. The FSCM can detect oscillator
failure at any point after the device has exited a Reset
or Sleep condition and the Oscillator Start-up Timer
(OST) has expired.
FIGURE 4-8:
The FSCM function is enabled by setting the FCMEN
bit in the Configuration Word (CONFIG). It is applicable
to all external clock options (LP, XT, HS, EC or RC
modes).
In the event of an external clock failure, the FSCM will
set the OSFIF bit (PIR2<7>) and generate an oscillator
fail interrupt if the OSFIE bit (PIE2<7>) is set. The
device will then switch the system clock to the internal
oscillator. The system clock will continue to come from
the internal oscillator unless the external clock recovers
and the Fail-Safe condition is exited.
© 2005 Microchip Technology Inc.
Program Counter
LFINTOSC
Oscillator
System Clock
Fail-Safe Clock Monitor
Primary
INTOSC
Clock
OSC1
OSC2
÷ 64
TWO-SPEED START-UP
FSCM BLOCK DIAGRAM
Q1
0
Detector
Q2
Clock
Fail
1
T
T
OST
Q3
1022 1023
PC
Clock
Failure
Detected
Q4
Preliminary
Q1
PIC16F917/916/914/913
The frequency of the internal oscillator will depend upon
the value contained in the IRCF bits (OSCCON<6:4>).
Upon entering the Fail-Safe condition, the OSTS bit
(OSCCON<3>) is automatically cleared to reflect that
the internal oscillator is active and the WDT is cleared.
The SCS bit (OSCCON<0>) is not updated. Enabling
FSCM does not affect the LTS bit.
The FSCM sample clock is generated by dividing the
INTOSC clock by 64. This will allow enough time
between FSCM sample clocks for a system clock edge
to occur. Figure 4-8 shows the FSCM block diagram.
On the rising edge of the sample clock, a monitoring
latch (CM = 0) will be cleared. On a falling edge of the
primary system clock, the monitoring latch will be set
(CM = 1). In the event that a falling edge of the sample
clock occurs, and the monitoring latch is not set, a clock
failure has been detected. The assigned internal
oscillator is enabled when FSCM is enabled as
reflected by the IRCF.
Q2
Note 1: Two-Speed
PC + 1
2: Primary clocks with a frequency ~488 Hz
enabled when the Fail-Safe Clock Monitor
mode is enabled.
will be considered failed by the FSCM. A
slow starting oscillator can cause an
FSCM interrupt.
Q3
Start-up
Q4
DS41250E-page 79
is
PC + 2
automatically
Q1