PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 82

• Manufacturer Part Number: PIC16F913-I/SP
• Description: 28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F913-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F917/916/914/913
4.7.1
The Fail-Safe condition is cleared after a Reset, the
execution of a SLEEP instruction, or a modification of
the SCS bit. While in Fail-Safe condition, the
PIC16F91X uses the internal oscillator as the system
without exiting the Fail-Safe condition.
The Fail-Safe condition must be cleared before the
OSFIF flag can be cleared.
FIGURE 4-9:
4.7.2
The FSCM is designed to detect oscillator failure at
any point after the device has exited a Reset or Sleep
condition and the Oscillator Start-up Timer (OST) has
expired. If the external clock is EC or RC mode,
monitoring will begin immediately following these
events.
For LP, XT or HS mode the external oscillator may
require a start-up time considerably longer than the
FSCM sample clock time, a false clock failure may be
detected (see Figure 4-9). To prevent this, the internal
oscillator is automatically configured as the system
clock and functions until the external clock is stable
(the OST has timed out). This is identical to
Two-Speed
oscillator is stable, the LFINTOSC returns to its role as
the FSCM source.
TABLE 4-2:
DS41250E-page 80
8Fh
90h
2007h
Legend:
Note 1:
Addr
Sample Clock
Note:
(1)
CM Output
2:
OSCFIF
OSCCON
OSCTUNE
CONFIG
System
Output
x = unknown, u = unchanged,
See Register 16-1 for operation of all Configuration Word bits.
See Register 4-1 for details.
FAIL-SAFE CONDITION CLEARING
RESET OR WAKE-UP FROM SLEEP
Clock
Name
Start-up
(Q)
The system clock is normally at a much higher frequency than the sample clock. The relative
frequencies in this example have been chosen for clarity.
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
FSCM TIMING DIAGRAM
Bit 7
CPD
mode.
—
—
IRCF2
Bit 6
CP
Once
—
CM Test
-
MCLRE PWRTE
IRCF1
= unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
the
Bit 5
—
external
IRCF0
TUN4
Bit 4
Preliminary
OSTS
WDTE
TUN3
Bit 3
(2)
CM Test
Note:
FOSC2
TUN2
Bit 2
HTS
Oscillator
Failure
Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit (OSCCON<3>) to verify the
oscillator start-up and system clock
switchover has successfully completed.
FOSC1
TUN1
Bit 1
LTS
FOSC0
TUN0
Bit 0
SCS
© 2005 Microchip Technology Inc.
Detected
Failure
-110 q000 -110 x000
---0 0000 ---u uuuu
POR, BOR
Value on:
CM Test
—
Value on
all other
Resets
—