PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 192

• Manufacturer Part Number: PIC16F913-I/SP
• Description: 28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F913-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F917/916/914/913
16.3.5
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired, then
OST is activated after the PWRT time-out has expired.
The total time-out will vary based on oscillator configu-
ration and PWRTE bit status. For example, in EC mode
with PWRTE bit erased (PWRT disabled), there will be
no time-out at all. Figure 16-4, Figure 16-5 and Figure
16-6 depict time-out sequences. The device can exe-
cute code from the INTOSC while OST is active, by
enabling Two-Speed Start-up or Fail-Safe Monitor (see
Section 4.6.2 “Two-Speed Start-up Sequence” and
Section 4.7 “Fail-Safe Clock Monitor”).
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 16-5). This is useful for testing purposes or
to synchronize more than one PIC16F917/916/914/913
device operating in parallel.
Table 16-5 shows the Reset conditions for some
special registers, while Table 16-5 shows the Reset
conditions for all the registers.
TABLE 16-1:
TABLE 16-2:
TABLE 16-3:
DS41250E-page 190
03h
8Eh
Legend:
Note 1:
XT, HS, LP
RC, EC, INTOSC
Note 1:
Legend: u = unchanged, x = unknown
Address
Oscillator Configuration
POR
0
1
u
u
u
u
STATUS
PCON
u = unchanged, x = unknown,
not used by BOR.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
LP mode with T1OSC disabled.
TIME-OUT SEQUENCE
(1)
Name
BOR
u
0
u
u
u
u
TIME-OUT IN VARIOUS SITUATIONS
PCON BITS AND THEIR SIGNIFICANCE
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Bit 7
IRP
—
TO
1
1
0
0
u
1
Bit 6
RP1
T
—
PWRT
PWRTE = 0
T
T
PWRT
PD
OSC
1
1
u
0
u
0
+ 1024 •
-
Bit 5
RPO
—
= unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are
Power-up
Power-on Reset
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during Sleep
SBOREN
Bit 4
TO
PWRTE = 1
1024 • T
Preliminary
—
Bit 3
OSC
PD
—
indicating that a Brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
16.3.6
The Power Control (PCON) register (address 8Eh) has
two Status bits to indicate what type of Reset that last
occurred.
Bit 0 is BOR (Brown-out Reset). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
(BOREN<1:0> = 00 in the Configuration Word register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., V
gone too low).
For more information, see Section 16.3.3 “Brown-Out
Reset (BOR)”.
T
Bit 2
PWRT
—
PWRTE = 0
Z
T
T
PWRT
OSC
+ 1024 •
Brown-out Reset
Bit 1
POR
POWER CONTROL (PCON)
REGISTER
Condition
DC
Bit 0
BOR
C
PWRTE = 1
1024 • T
© 2005 Microchip Technology Inc.
—
0001 1xxx
--01 --qq
POR, BOR
Value on
OSC
Wake-up from
1024 • T
DD
000q quuu
--0u --uu
Sleep
Resets
Value on
all other
may have
—
OSC
(1)