PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 144

• Manufacturer Part Number: PIC16F913-I/SP
• Description: 28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F913-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F917/916/914/913
TABLE 11-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
11.4.2
The operation of the Synchronous Master and Slave
modes is identical, except in the case of the Sleep
mode. Bit SREN is a “don't care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
Sleep. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE bit is set, the interrupt generated
will wake the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
TABLE 11-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
DS41250E-page 142
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
19h
8Ch
98h
99h
Legend:
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
1Ah
8Ch
98h
99h
Legend:
Address
Address
x = unknown,
x = unknown,
USART SYNCHRONOUS SLAVE
RECEPTION
INTCON
PIR1
RCSTA
RCREG
PIE1
TXSTA
SPBRG
INTCON
PIR1
RCSTA
TXREG
PIE1
TXSTA
SPBRG
Name
Name
USART Receive Data Register
Baud Rate Generator Register
USART Transmit Data Register
Baud Rate Generator Register
CSRC
SPEN
CSRC
SPEN
EEIF
EEIE
Bit 7
Bit 7
EEIF
EEIE
-
-
GIE
GIE
= unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
= unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
PEIE
ADIF
ADIE
Bit 6
RX9
TX9
PEIE
ADIF
ADIE
Bit 6
RX9
TX9
SREN
TXEN
RCIE
RCIF
SREN
TXEN
Bit 5
T0IE
RCIE
RCIF
Bit 5
T0IE
CREN ADDEN
SYNC
CREN ADDEN
SYNC
INTE
INTE
Bit 4
TXIF
TXIE
Bit 4
TXIF
TXIE
Preliminary
SSPIE
SSPIE
SSPIF
SSPIF
RBIE
RBIE
Bit 3
Bit 3
—
—
When setting up a Synchronous Slave Reception,
follow these steps:
1.
2.
3.
4.
5.
6.
7.
8.
9.
CCP1IF TMR2IF TMR1IF 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
BRGH
BRGH
FERR
FERR
Bit 2
T0IF
Bit 2
T0IF
Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
bit CREN.
If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
OERR
TRMT
OERR
TRMT
Bit 1
INTF
INTF
Bit 1
RX9D
TX9D
Bit 0
RBIF
RX9D
TX9D
Bit 0
RBIF
© 2005 Microchip Technology Inc.
0000 000x
0000 0000
0000 -010
0000 0000
0000 000x
POR, BOR
0000 000x 0000 000x
0000 000x 0000 000x
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
Value on:
POR, BOR
Value on:
0000 0000
0000 000x
0000 0000
0000 0000
0000 -010
0000 0000
0000 000x
Value on
all other
Value on
all other
Resets
Resets