PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 198

• Manufacturer Part Number: PIC16F913-I/SP
• Description: 28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F913-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 25
• Interface: I2C/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 7K Bytes
• Ram Size: 256 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F917/916/914/913
16.4.1
External interrupt on RB0/INT/SEG0 pin is edge-trig-
gered; either rising if the INTEDG bit (OPTION<6>) is
set, or falling, if the INTEDG bit is clear. When a valid
edge appears on the RB0/INT/SEG0 pin, the INTF bit
(INTCON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the Interrupt Service
Routine
RB0/INT/SEG0 interrupt can wake-up the processor
from Sleep if the INTE bit was set prior to going into
Sleep. The status of the GIE bit decides whether or not
the processor branches to the interrupt vector following
wake-up (0004h). See Section 16.7 “Power-Down
Mode (Sleep)” for details on Sleep and Figure 16-10
for
RB0/INT/SEG0 interrupt.
FIGURE 16-7:
DS41250E-page 196
timing
before
RB0/INT/SEG0 INTERRUPT
IOC-RB4
IOC-RB5
IOC-RB6
IOC-RB7
TMR2IF
TMR2IE
TMR1IE
TMR1IF
CCP1IF
CCP1IE
CCP2IF
CCP2IE
OSFIF
OSFIE
SSPIE
LCDIF
LCDIE
SSPIF
IOCB4
IOCB5
IOCB6
IOCB7
LVDIF
LVDIE
of
RCIF
RCIE
ADIF
ADIE
C1IF
C1IE
C2IF
C2IE
EEIF
EEIE
TXIF
TXIE
re-enabling
wake-up
INTERRUPT LOGIC
*
from
this
Sleep
interrupt.
through
TMR0IF
TMR0IE
The
RBIE
INTF
INTE
RBIF
PEIF
PEIE
Preliminary
GIE
16.4.2
An overflow (FFh
the T0IF (INTCON<2>) bit. The interrupt can be
enabled/disabled
(INTCON<5>) bit. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
16.4.3
An input change on PORTB change sets the RBIF
(INTCON<0>)
enabled/disabled
(INTCON<3>) bit. Plus, individual pins can be config-
ured through the IOCB register.
Note:
* Only available on the PIC16F914/917.
TMR0 INTERRUPT
PORTB INTERRUPT
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF
interrupt flag may not get set.
bit.
Wake-up (If in Sleep mode)
by
00h) in the TMR0 register will set
by
© 2005 Microchip Technology Inc.
The
setting/clearing
Interrupt to CPU
setting/clearing
interrupt
the
can
RBIE
T0IE
be