PIC16F913-I/SP Microchip Technology Inc., PIC16F913-I/SP Datasheet - Page 181

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PIC16F913-I/SP

Manufacturer Part Number
PIC16F913-I/SP
Description
28 PIN, 7 KB FLASH, 352 RAM, 25 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC16F913-I/SP

A/d Inputs
5-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
25
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
7K Bytes
Ram Size
256 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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Manufacturer
Quantity
Price
Part Number:
PIC16F913-I/SP
Manufacturer:
TI
Quantity:
212
15.1
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC5/T1CKI/CCP1/SEG10. An event is defined
as one of the following:
• Every falling edge
• Every rising edge
• Every 4th rising edge
• Every 16th rising edge
The type of event is configured by control bits
CCP1M<3:0> (CCPxCON<3:0>). When a capture is
made, the interrupt request flag bit CCP1IF (PIR1<2>)
is set. The interrupt flag must be cleared in software. If
another capture occurs before the value in register
CCPR1 is read, the old captured value is overwritten by
the new value.
15.1.1
In Capture mode, the RC5/T1CKI/CCP1/SEG10 pin
should be configured as an input by setting the
TRISC<5> bit.
FIGURE 15-3:
15.1.2
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
15.1.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF, following any such
change in Operating mode.
© 2005 Microchip Technology Inc.
CCP1/SEG10
RC5/T1CKI/
Note:
pin
Capture Mode
Qs
edge detect
CCP PIN CONFIGURATION
If the RC5/T1CKI/CCP1/SEG10 pin is
configured as an output, a write to the port
can cause a capture condition.
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT
Prescaler
1, 4, 16
and
CCP1CON<3:0>
Set Flag bit CCP1IF
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
(PIR1<2>)
Capture
Enable
CCPR1H
TMR1H
CCPR1L
TMR1L
Preliminary
PIC16F917/916/914/913
15.1.4
There are four prescaler settings, specified by bits
CCP1M<3:0>. Whenever the CCP module is turned
off, or the CCP module is not in Capture mode, the
prescaler counter is cleared. Any Reset will clear the
prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 15-1 shows the recom-
mended method for switching between capture pre-
scalers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 15-1:
CLRF
MOVLW
MOVWF
CCP1CON
NEW_CAPT_PS ; Load the W reg with
CCP1CON
CCP PRESCALER
CHANGING BETWEEN
CAPTURE PRESCALERS
; Turn CCP module off
; the new prescaler
; move value and CCP ON
; Load CCP1CON with this
; value
DS41250E-page 179

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